v54c316162 ETC-unknow, v54c316162 Datasheet - Page 4

• Manufacturer Part Number: v54c316162
• Description: 200/183/166/143 Volt, Refresh Ultra High Performance Sdram Banks 512kbit
• Manufacturer: ETC-unknow

M O S E L V I T E L I C
Signal Pin Description
V54C316162V Rev.2.9 September 2001
Pin
CLK
CKE
CS
RAS
CAS
WE
A
BA
I/O
UDQM, LDQM
VDD/VSS
VDDQ/VSSQ
NC
0
-A
1
-I/O
10
16
Name
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address
Bank Select
Data Input/Output
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
Input Function
System clock input. Active on the positive rising edge to sample all inptus
Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self
refresh mode
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
Latches row addresses on the positive edge of CLK with RAS low.
Enables row access & precharge
Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
Enables write operation
During a bank activate command, A
During a read or write command, A
addition to the column address A
define the bank to be precharged. A
during a precharge cycle, If A
if A
high, all banks will be precharged.
Selects which bank to activate. BA low select bank A and high selects
bank B
Data inputs/output are multiplexed on the same pins
Makes data output Hi-Z. Blocks data input when DQM is active
Power Supply. +3.3V ± 0.3V/ground
Provides isolated power/ground to DQs for improved noise immunity
10
4
is low, the BA is used to decide which bank to precharge. If A
10
is high, both bank will be precharged ,
10
0
is used to invoke auto precharge BA
10
0
-A
-A
is low, auto precharge is disabled
7
10
defines the column address. In
defines the row address.
V54C316162V
10
is