FS6370-01 American Microsystems, Inc., FS6370-01 Datasheet - Page 3

• Manufacturer Part Number: FS6370-01
• Description: EePROM Programmable 3-pll Clock Generator ic
• Manufacturer: American Microsystems, Inc.

The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
3.1.1
The Reference Divider is designed for low phase jitter.
The divider accepts the output of the reference oscillator
and provides a divided-down frequency to the PFD. The
Reference Divider is an 8-bit divider, and can be pro-
grammed for any modulus from 1 to 255 by programming
the equivalent binary value. A divide-by-256 can also be
achieved by programming the eight bits to 00h.
3.1.2
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the program-
mable Feedback Divider because of the high speeds at
which the VCO can operate. The dual-modulus technique
insures reliable operation at any speed that the VCO can
achieve and reduces the overall power consumption of
the divider.
For example, a fixed divide-by-eight prescaler could have
been used in the Feedback Divider. Unfortunately, a di-
vide-by-eight would limit the effective modulus of the en-
tire feedback divider to multiples of eight. This limitation
would restrict the ability of the PLL to achieve a desired
input-frequency-to-output-frequency ratio without making
both the Reference and Feedback Divider values com-
paratively large. Generally, very large values are unde-
sirable as they degrade the bandwidth of the PLL, in-
creasing phase jitter and acquisition time.
To understand the operation of the feedback divider, refer
to Figure 4. The M-counter (with a modulus always equal
to M) is cascaded with the dual-modulus prescaler. The
A-counter controls the modulus of the prescaler. If the
value programmed into the A-counter is A, the prescaler
will be set to divide by N+1 for A prescaler outputs.
Thereafter, the prescaler divides by N until the M-counter
output resets the A-counter, and the cycle begins again.
Note that N=8, and A and M are binary numbers.
Reference Divider
Feedback Divider
f
VCO
f
REF
æ
ç ç
è
N
N
F
R
ö
÷ ÷
ø
.
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
3
Figure 4: Feedback Divider
Suppose that the A-counter is programmed to zero. The
modulus of the prescaler will always be fixed at N; and
the entire modulus of the feedback divider becomes M N.
Next, suppose that the A-counter is programmed to a
one. This causes the prescaler to switch to a divide-by-
N+1 for its first divide cycle and then revert to a divide-by-
N. In effect, the A-counter absorbs (or “swallows”) one
extra clock during the entire cycle of the Feedback Di-
vider. The overall modulus is now seen to be equal to
M N+1.
This example can be extended to show that the Feed-
back Divider modulus is equal to M N+A, where A≤M.
3.1.3
For proper operation of the Feedback Divider, the A-
counter must be programmed only for values that are
less than or equal to the M-counter. Therefore, not all
divider moduli below 56 are available for use. This is
shown in Table 2.
Above a modulus of 56, the Feedback Divider can be
programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
M-COUNTER:
FBKDIV[10:3]
00000001
00000010
00000011
00000100
00000101
00000110
00000111
f
VCO
Feedback Divider Programming
000
Prescaler
16
24
32
40
48
56
FBKDIV[2:0]
Modulus
8
Counter
Dual
A
001
17
25
33
41
49
57
9
FEEDBACK DIVIDER MODULUS
A-COUNTER: FBKDIV[2:0]
010
18
26
34
42
50
58
-
011
FS6370-01
FS6370-01
FS6370-01
FS6370-01
27
35
43
51
59
-
-
FBKDIV[10:3]
Counter
M
100
36
44
52
60
-
-
-
101
45
53
61
-
-
-
-
110
54
62
-
-
-
-
-
f
PD
111
63
-
-
-
-
-
-