CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet
CYNSE10128-083FGCI
Related parts for CYNSE10128-083FGCI
CYNSE10128-083FGCI Summary of contents
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... Ayama™ 10000 Network Search Engine Cypress Semiconductor Corporation Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY • 3901 North First Street • San Jose CYNSE10512 CYNSE10256 CYNSE10128 , CA 95134 • 408-943-2600 Revised July 13, 2004 [+] Feedback [+] Feedback ...
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... Multi-Hit Description .................................................................................................................. 41 5.6 Clocks ....................................................................................................................................... 42 5.7 Phase-Locked Loop .................................................................................................................. 43 5.8 Pipeline Latency ........................................................................................................................ 43 5.9 DQ Bus Encoding of Ayama 10000 Address Space ................................................................. 43 5.9.1 Addressing the Data Array, Mask Array and External SRAM ......................................................... 44 5.9.2 Addressing the Internal Registers ................................................................................................... 45 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY TABLE OF CONTENTS CYNSE10512 CYNSE10256 CYNSE10128 Page 2 of 153 [+] Feedback [+] Feedback ...
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... SRAM Write with Table(s) Consisting Devices ........................................................... 131 6.8 Timing Sequences for Back-to-Back Operations .................................................................... 133 6.9 Full Signal Timing Diagram ..................................................................................................... 134 7.0 JTAG (IEEE 1149.1) ..................................................................................................................... 135 8.0 POWER CONSUMPTION ............................................................................................................ 136 9.0 ELECTRICAL SPECIFICATIONS ................................................................................................ 137 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY TABLE OF CONTENTS (continued) CYNSE10512 CYNSE10256 CYNSE10128 Page 3 of 153 [+] Feedback [+] Feedback ...
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... AC Timing Parameters and Waveforms with CLK1X ........................................................... 140 10.3 AC Test Conditions and Output Loads ................................................................................. 143 10.3.1 LVCMOS 2.5V/1.8V .................................................................................................................... 143 10.3.2 HSTL I/II ...................................................................................................................................... 144 11.0 PIN ASSIGNMENT AND PINOUT DIAGRAM ........................................................................... 145 12.0 PACKAGE DIAGRAMS ............................................................................................................. 151 13.0 ORDERING INFORMATION ...................................................................................................... 151 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY TABLE OF CONTENTS (continued) CYNSE10512 CYNSE10256 CYNSE10128 Page 4 of 153 [+] Feedback [+] Feedback ...
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... Figure 6-6. Multiwidth Configurations Using CYNSE10512 as an Example .......................................... 58 Figure 6-7. Timing Diagram for Mixed MultiSearch (One Device) ......................................................... 59 Figure 6-8. Multiwidth Configurations Using CYNSE10512 as an Example .......................................... 60 Figure 6-9. Hardware Diagram for a Table with Eight Devices.............................................................. 61 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY LIST OF FIGURES CYNSE10512 CYNSE10256 CYNSE10128 Page 5 of 153 [+] Feedback [+] Feedback ...
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... Figure 6-56. Timing Diagram of 72-bit Learn from DQ Bus and CMPR Registers (One Device) ........ 114 Figure 6-57. Timing Diagram of 288-bit Learn from DQ Bus and CMPR Registers (One Device) ...... 115 Figure 6-58. Timing Diagram of 576-bit Learn from DQ Bus (One Device) ......................................... 116 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY LIST OF FIGURES (continued) CYNSE10512 CYNSE10256 CYNSE10128 Page 6 of 153 [+] Feedback [+] Feedback ...
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... Figure 10-9. Test Condition of HSTL II I/O Output Load Equivalent.................................................... 144 Figure 10-10. Test Condition of HSTLI/II I/O High-Z Output Load Equivalent..................................... 144 Figure 11-1. Pinout Diagram (Top View) ............................................................................................. 145 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY LIST OF FIGURES (continued) , LDEV = 1 (binary)) ................................... 118 (binary) CYNSE10512 CYNSE10256 CYNSE10128 Page 7 of 153 [+] Feedback [+] Feedback ...
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... Table 7-1. Supported Operations ....................................................................................................... 135 Table 7-2. TAP Device ID Register ..................................................................................................... 135 Table 9-1. DC Electrical Characteristics for Ayama 10000 ................................................................. 137 Table 9-2. Operating Conditions for Ayama 10000 ............................................................................ 137 Table 10-1. AC Timing Parameters with CLK2X ................................................................................ 138 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY LIST OF TABLES CYNSE10512 CYNSE10256 CYNSE10128 Page 8 of 153 [+] Feedback [+] Feedback ...
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... Table 10-4. 2.5V / 1.8V AC Table for LVCMOS Test Condition of Ayama 10000 .............................. 143 Table 10-5. 1.5V AC Table for HSTL Test Condition of Ayama 10000 .............................................. 144 Table 11-1. Pin Assignment ................................................................................................................ 146 Table 13-1. Ordering Information ........................................................................................................ 151 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY LIST OF TABLES (continued) CYNSE10512 CYNSE10256 CYNSE10128 Page 9 of 153 [+] Feedback [+] Feedback ...
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... CYNSE10128 — 64K entries in 72-bit configuration — 32K entries in 144-bit configuration — 16K entries in 288-bit configuration — ...
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... Figure 2-1. Ayama™ 10000 Block Diagram CYNSE10512 CYNSE10256 CYNSE10128 TMS TCK TAP TRST_L Controller TDI TDO SADR[N:0], Pipeline OE_L for and CYNSE10512, SRAM WE_L 24 for CYNSE10256, Interface CE_L 23 for Control CYNSE10128 ALE_L MULTI_HIT FULO[1:0]/LHO_1[1:0] LHO[1:0]/LHO_0[1:0] BHO[2:0] SSF SSV Page 11 of 153 [+] Feedback [+] Feedback ...
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... Figure 2-2. Example of Switch/Router Implementation Using Ayama 10000 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Program Memory Ayama 10000 Host Bank ASIC Ayama 10000 Bank Host ASIC SRAM Bank CYNSE10512 CYNSE10256 CYNSE10128 NSE Subsystem SRAM Bank Associative Mode or Index Mode Page 12 of 153 [+] Feedback [+] Feedback ...
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... Data Array, Mask Array and Table Widths The Ayama 10000 device consists of M × 72-bit (M = 256K for CYNSE10512, 128K for CYNSE10256, 64K for CYNSE10128) storage cells referred to as data bits. There is also a mask cell corresponding to each data cell. A database entry includes both the data and mask cells ...
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... CYNSE10512 CYNSE10256 CYNSE10128 288-bit configuration 262144 for CYNSE10512 131072 for CYNSE10256 65536 for CYNSE10128 Match Result Page 14 of 153 [+] Feedback [+] Feedback ...
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... This signal is valid only after the device is fully initialized. ASIC Interface / Command and Data Buses (LVCMOS or HSTL I/II) CMD[10:0] I Command Bus. Bit[10:2] contains the command parameters and Bit[1:0] specifies the command. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Description CYNSE10512 CYNSE10256 CYNSE10128 ), the device DDQ_ASIC . DDQ_ASIC Page 15 of 153 [+] Feedback [+] Feedback ...
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... SRAM Address. This bus contains address lines to access off-chip SRAMs that contain associative data cascaded system of multiple Ayama 10000 NSEs, each corre- sponding SADR bit from all cascaded devices must be tied together for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. [5] CE_L T SRAM Chip Enable ...
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... Require an external pull-down resistor such as 47K 5. These signals will output at the rising edge of CLK2X (both rising and falling edges of CLK1X MultiSearch operation. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Description Ω Ω or 100K . CYNSE10512 CYNSE10256 CYNSE10128 Ω Ω to 47K . Page 17 of 153 [+] Feedback [+] Feedback ...
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... MSPS Yes Yes Yes Yes Data from CMPR Register or DQ Bus; Target Data or Mask Array; Supports all table widths BMR Register x72, x144, x288, x576 128/64/32 2Kx72-bit Blocks for CYNSE10512/256/128 respectively CYNSE10512 CYNSE10256 CYNSE10128 Enhanced Page 18 of 153 [+] Feedback [+] Feedback ...
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... Parity Register 2K Block 0 NFA Register Priority Register Parity Register Block 1 2K NFA Register Priority Register Parity Register 2K Block N NFA Register 72 Bits Mini-Key Register Figure 5-2. Mini-Key Register Contents CYNSE10512 CYNSE10256 CYNSE10128 N = 127 for CYNSE10512 63 for CYNSE10256 31 for CYNSE10128 2K Page 19 of 153 [+] Feedback [+] Feedback ...
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... PARERR_L signal goes Low 4 cycles after the error is detected. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY V0 512 x 72 Sub-Block 0 V1 Sub-Block 1 V2 Sub-Block 2 V3 Sub-Block 3 CYNSE10512 CYNSE10256 CYNSE10128 N = 127 for CYNSE10512 63 for CYNSE10256 31 for CYNSE10128 th cycle of latency Page 20 of 153 [+] Feedback [+] Feedback ...
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... PARITY register to obtain the location, reading the BPAR registers to locate blocks that has the error and then fixing those locations. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY cycle cycle cycle cycle incorrect value for PAR[1] T+3 T+4 T+2 th cycle of latency. For example, with TLSZ set to “00” and the CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle cycle Page 21 of 153 [+] Feedback [+] Feedback ...
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... When MultiSearch is activated, the Core is divided into two separate arrays. Each array is organized into 64/32/16 blocks (corresponds to CYNSE10512/CYNSE10256/CYNSE10128, respectively 72-bit entries. Each block can be configured width x72, x144, x288, or x576. This separation allows a Search operation to simultaneously perform the search across both arrays ...
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... CMPR 1: GMR GMR CMPR 1: GMR GMR GMR GMR+1 CYNSE10512 CYNSE10256 CYNSE10128 Array 1 Key SRR CMPR CMPR CMPR CMPR ...
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... Search operation does not result in a Search Hit. Refer to Section 5.3 for more information. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY CASCADE Ayama 10000 CASCADE CASCADE Ayama 10000 CASCADE CASCADE Ayama 10000 CASCADE CASCADE Ayama 10000 CASCADE Figure 5-7. Ayama 10000 I/O Interfaces CYNSE10512 CYNSE10256 CYNSE10128 To SRAMs (Associative ASIC (Index) Page 24 of 153 [+] Feedback [+] Feedback ...
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... See Section 5.4.12. Search Result Register. These registers provide information of the next-free entry when the device is in the Enhanced mode. (Non-Enhanced mode uses the NFA register to store the next-free entry information.) See Section 5.4.13. CYNSE10512 CYNSE10256 CYNSE10128 Page 25 of 153 [+] Feedback [+] Feedback ...
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... There is one BNFA per block. See Section 5.4.17. Block Priority Register Aliases. These locations are aliases for the corre- sponding BPRx. See Section 5.4.18. Address 72 72 index 143 CYNSE10512 CYNSE10256 CYNSE10128 Page 26 of 153 [+] Feedback [+] Feedback ...
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... for CYNSE10512 Figure 5-10. Search Successful Register CYNSE10512 CYNSE10256 CYNSE10128 for CYNSE10256 for CYNSE10128 INDEX Page 27 of 153 [+] Feedback [+] Feedback ...
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... Index. This is the address of the 72-bit entry where a successful search occurs. This index is updated if the device is either a local or global winner in a Search operation for CYNSE10512, 16 for CYNSE10256, 15 for CYNSE10128 hit occurs in a 144-bit table, the least-significant bit (LSB) is cleared to 0. ...
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... SADR, CE_L, WE_L, and ALE_L signals. In cycles where none of the Ayama 10000 devices in a cascade drive these signals, this device drives the signals as follows: For CYNSE10512: SADR = 0x1FFFFFF For CYNSE10256: SADR = 0xFFFFFF For CYNSE10128: SADR = 0x7FFFFF For CYNSE10512/256/128: CE_L = 1 WE_L = 1 ALE_L = 1 The device with this field set to 1 always drives OE_L ...
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... Read operation. The NSE will automatically increment the value by one after each successive Read of the data or mask array. It must be reinitialized before the next Burst- Read operation for CYNSE10512, 16 for CYNSE10256, 15 for CYNSE10128. [18:M] Reserved for CYNSE10512, 17 for CYNSE10256, 16 for CYNSE10128. ...
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... Burst-Write operation. The NSE will automatically increment the value by one after each successive Write of the data or mask array. It must be reinitialized before the next Burst-Write operation for CYNSE10512, 16 for CYNSE10256, 15 for CYNSE10128. Reserved for CYNSE10512, 17 for CYNSE10256, 16 for CYNSE10128. ...
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... Bit[1:0] configures the first partition, Bit[3:2] configures the second partition and so on. Bit [15:0] of this register is aliased in Bit[24:9] of the Command register. Modifi- cation to Bit[15:0] of this field will affect the CFGA field in the Command register and vice versa. Reserved. CYNSE10512 CYNSE10256 CYNSE10128 ...
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... Command and DQ Bus I/Os. The following output signals are part of this group: DQ, ACK, EOT, SSF, SSV, PAR, PARERR_L, MULTI_HIT, and FULL. Refer to IOJTAG above for I/O drive strength encoding. Reserved. Reserved. This field must be set to 0. CYNSE10512 CYNSE10256 CYNSE10128 1.8V) Page 33 of 153 [+] Feedback ...
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... Core. Note that if another Parity operation is performed, this field is updated based upon that operation for CYNSE10512, 16 for CYNSE10256 (bit [17] is reserved), 15 for CYNSE10128 (bits [17:16] are reserved). Bit[18] is used to indicate whether a mask (=1) or data (=0) entry contained the error. [27:19] Reserved ...
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... Soft Priority Comparison Flag. When set to 1, Search comparison is with entries that has Soft Priority value equal to or higher (lower priority) than PRIORITY. When set to 0, comparison is only with equal value. Reserved. CYNSE10512 CYNSE10256 CYNSE10128 Page 35 of 153 [+] Feedback [+] Feedback ...
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... Index. This field contains the Hit or Miss index inside the Core for CYNSE10512, 16 for CYNSE10256, 15 for CYNSE10128. Reserved for CYNSE10512, 17 for CYNSE10256, 16 for CYNSE10128. Mini-Key. This field contains a copy of the Mini-Key value selected for the Search operation. The value comes from the selected CPR. ...
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... Mini-Key in the selected CPR by the command. If there is a match, the associated block is enabled to participate in the operation. Mini-Key #2. See Mini-Key #3 description. Mini-Key #1. See Mini-Key #3 description. Mini-Key #0. See Mini-Key #3 description. Reserved. CYNSE10512 CYNSE10256 CYNSE10128 Page 37 of 153 [+] Feedback [+] Feedback ...
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... V #2. See V #3 description. V1 [62 #1. See V #3 description. V0 [63 #0. See V #3 description. [71:64] Reserved. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY PRIORITY0 PRIORITY1 Figure 5-23. Block Priority Register Description CYNSE10512 CYNSE10256 CYNSE10128 PRIORITY2 PRIORITY3 Page 38 of 153 [+] Feedback [+] Feedback ...
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... Multi Free Entry in Sub-block #2. See MULTI3 description. F2 [31] 0 Free Entry in Sub-block #2. See F3 description. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Figure 5-24. Block Parity Register Description NFA1 Figure 5-25. Block NFA Register Description CYNSE10512 CYNSE10256 CYNSE10128 NFA2 NFA3 Page 39 of 153 [+] Feedback [+] Feedback ...
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... Figure 5-26. Block Priority Register Aliases Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Description PRIORITY0 PRIORITY1 CYNSE10512 CYNSE10256 CYNSE10128 PRIORITY2 PRIORITY3 Page 40 of 153 [+] Feedback [+] Feedback ...
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... HLAT. In the Enhanced mode, the Multi-Hit signal is valid at the same time as SSV. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Description Reserved. Priority #0. Reserved. V #0. Reserved. Description Reserved. Priority #1. Reserved. V #1. Reserved. Description Reserved. Priority #2. Reserved. V #2. Reserved. Description Priority #3. Reserved. V #3. Reserved. CYNSE10512 CYNSE10256 CYNSE10128 Page 41 of 153 [+] Feedback [+] Feedback ...
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... Any reference to “CLK” cycles means one cycle of CLK. 8. Only supported in Non-Enhanced mode. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY “Cycle B End” Figure 5-28. Ayama 10000 Clocks (CLK1X) CYNSE10512 CYNSE10256 CYNSE10128 Page 42 of 153 [+] Feedback [+] Feedback ...
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... INDEX field as the address for a Read, Write and Learn operations. Indirect Read operation on the internal registers will return undefined values. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Total Search CLK1X Cycle Latency Invalid CYNSE10512 CYNSE10256 CYNSE10128 Maximum Operating Speed (CLK1X/CLK2X) 83/166 MHz 100/200 MHz 133/266 MHz Invalid Page 43 of 153 [+] Feedback [+] Feedback ...
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... When MultiSearch feature is enabled, SADR[M+8] is not used and SADR[M] will indicate Array0 output indicate Array 1 output. 10 for CYNSE10512 for CYNSE10256 for CYNSE10128. 11. Non-Enhanced mode uses NFA register. Enhanced mode uses SRR register. 12. SSR[2:0] is OR-ed with DQ[2:0] to generate the SADR[2:0] values. ...
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... Description Enhanced Mode Non-Enhanced with MSE = 0 1 2-8 9- Yes No Yes Yes No No Yes No Yes No Yes Yes No No Yes No CYNSE10512 CYNSE10256 CYNSE10128 BLKNUM REGSEL Enhanced Mode with MSE = 1 9-31 1 2-8 9-31 No Yes Yes No [13] [13] [13] No Yes No No [13] [13] [13] [13] No Yes Yes ...
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... LHI Ayama 10000 #5 LHO[ LHI LHI Ayama 10000 #6 LHO[ LHI LHI Ayama 10000 #7 LHO[1] LHO[0] CYNSE10512 CYNSE10256 CYNSE10128 SRAM LHO[ LHO[ LHO[ BHO[0] BHO[0] BHO[1] BHO[1] BHO[2] BHO[2] Page 46 of 153 ...
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... BHO[0] BHI[2] BHI[1] BHI[0] Block of 8 Ayama 10000s Block 2 (devices 16–23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] Block of 7 Ayama 10000s Block 3 (devices 24–30) BHO[2] BHO[1] BHO[0] Figure 5-33. Depth Cascading 4 Blocks CYNSE10512 CYNSE10256 CYNSE10128 SRAM GND Page 47 of 153 [+] Feedback [+] Feedback ...
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... FULI FULI Ayama 10000 FULO[ FULI FULI Ayama 10000 FULO[ FULI FULI Ayama 10000 FULO[1] FULO[0] CYNSE10512 CYNSE10256 CYNSE10128 VDDQ FULO[0] FULL VDDQ FULO[0] FULL VDDQ FULL VDDQ FULL VDDQ ...
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... DDQ after the clock signal is stable, then drive high. RSTL VDDQ asynchronous delay PLL lock time, 0 RSTL Figure 5-35. Proper Power-up Sequence CYNSE10512 CYNSE10256 CYNSE10128 ) level reaches 90% point. DD when V is stable. TRST_L can be tied to DD Page 49 of 153 [+] Feedback [+] Feedback ...
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... CONFIDENTIAL PRELIMINARY Description EADR[2:0] [14] 0 EADR[2:0] [14] 0 EADR[2:0] [14] SSR[2:0] EADR[2:0] [14] 0=x72 0 1=x144 CYNSE10512 CYNSE10256 CYNSE10128 Single Burst 0 = Single GMR[2: Burst 0=x72 or x144 GMR[2:0] 1=x288 (first cycle 0=x288 (last cycle) CMPR[3:0] CMPR[3: Page 50 of 153 ...
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... EADR[1:0] [14] 0 EADR[1:0] [14] 1=Multi-Search SSR[2:0] 0 EADR[1:0] [14] 00: x72; 01: x144; 1X:x288/x576 0 (all except last cycle); 0X:x288/x576 (last cycle) Description CYNSE10512 CYNSE10256 CYNSE10128 Single Burst 0 = Single GMR[2: Burst 0=x72 or x144 1=x288/x576 (all except GMR[2:0] last cycle ...
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... The host ASIC selects the Ayama 10000 device for which ID[4:0] matches the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the Ayama 10000 with the LDEV bit set. The host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM. ...
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... Note that when Parity feature is enabled masks will be ignored and all bits will be written as presented in the DQ bus. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY cycle cycle cycle cycle cycle cycle cycle cycle cycle Data0 0 Data1 0 Data2 CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle Data3 0 Page 53 of 153 [+] Feedback [+] Feedback ...
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... CMD[5:3]}. For SRAM WRITEs, the host ASIC must supply the SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6]. The host ASIC sets CMD[ for a normal Write. • Cycle 1B:The host ASIC continues to apply the Write instruction to CMD[1:0] (CMD[ using CMDV = 1, and the address supplied on the DQ bus ...
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... Mini-Key(s) selected by the GMR field. For Ayama 10512, this corresponds to 128 parallel locations (128 blocks, 1 location per block). Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY cycle cycle cycle cycle cycle cycle Write A B Address Data0 Data1 Data2 Data3 CYNSE10512 CYNSE10256 CYNSE10128 6 DQ should be driven to zero in this cycle 0 Page 55 of 153 [+] Feedback [+] Feedback ...
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... Max. Table Size (With Max. Number of Devices Not Applicable N/2 x 144 N/4 x 288 N/8 x 576 N = 2048K for CYNSE10512, 1024K for CYNSE10256, 512K for CYNSE10128 N/2 x 144 N/4 x 288 N/8 x 576 N = 7936K for CYNSE10512, 3968K for CYNSE10256, 1984K for CYNSE10128 Reserved Page 56 of 153 [+] Feedback [+] Feedback ...
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... SSF 0 HLAT = 001 (binary), TLSZ = 00 (binary), LRAM = 1 (binary), LDEV = 1 (binary for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 Figure 6-5. Timing Diagram for Mixed Single Search (One Device) TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary) for this particular example. The following is the sequence of operation for a single Search command (also refer to Subsection 6.2, “Command Bus Param- eters,” ...
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... L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. The latency of the Search from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ[1:0] = 01). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-5 ...
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... GMR pair for use in this Search operation. CMD[7:6] signals must be driven with the same bits that will be driven on SADR[24:23] for CYNSE10512, SADR[23:22] for CYNSE10256, SADR[22:21] for CYNSE10128 by this device if it has a hit. CMD[8] must be driven high for MultiSearch operation. ...
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... La and Lb will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. The latency of the Search from command to SRAM access cycle is 5 for a single device ( eight devices) configuration in the table (TLSZ[1:0] = 01) ...
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... LHI LHI Ayama 10000 #6 LHO[ LHI LHI Ayama 10000 #7 LHO[1] LHO[0] 2 Miss Hit Miss Miss CYNSE10512 CYNSE10256 CYNSE10128 SRAM LHO[ LHO[ BHO[0] BHO[0] BHO[1] BHO[1] BHO[2] BHO[ Hit ...
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... OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CFG[N:0] are all zeroes for Non-Enhanced Mode for CYNSE10512, 31 for CYNSE10256, 15 for CYNSE10128 NES = 00 (binary) in each block for Enhanced Mode. HLAT = 010 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. ...
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... OE_L SSV z z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CFG[N:0] are all zeroes for Non-Enhanced Mode for CYNSE10512, 31 for CYNSE10256, 15 for CYNSE10128. NES = 00 (binary) in each block for Enhanced Mode. HLAT = 010 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
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... GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 by this device if it has a hit. — DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared. ...
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... SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. The global winning device will drive the bus in a specific cycle global miss cycle, the device with LRAM = 1 (default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the default driver for such missed cycles ...
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... LHI_1_L LHO_1_L[0] LHO_0[0] V DDQ_ASIC LHI_1_L LHO_1_L[0] LHO_0[ LHI_1_L LHO_1_L[1] LHO_1_L[0] LHO_0[1] LHO_0[0] CYNSE10512 CYNSE10256 CYNSE10128 V DDQ_ASIC SRAM LHI_0 LHO_0[1] LHO_0[0] V DDQ_ASIC LHI_0 LHO_0[1] LHO_0[ LHI_0 ...
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... Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY 2 3 Miss Hit Miss Miss Miss Hit Hit Miss Miss Miss Miss Miss Hit Miss Hit Hit CYNSE10512 CYNSE10256 CYNSE10128 4 5 Hit Hit Hit Miss Miss Miss Miss Miss Miss Miss Miss Miss Page 67 of 153 [+] Feedback [+] Feedback ...
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... SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ respectively of the entire LHI bus. Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal. ...
Page 69
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ respectively of the entire LHI bus. Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal. ...
Page 70
... SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary). Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ respectively of the entire LHI bus. Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal. ...
Page 71
... CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[7:6] signals must be driven with the same bits that will be driven on SADR[24:23] for CYNSE10512, SADR[23:22] for CYNSE10256, SADR[22:21] for CYNSE10128 by this device if it has a hit. CMD[8] must be set to logic 1, and CMD[9] must be set to logic 0. ...
Page 72
... For Non-Enhanced Mode, CFG[63:0] = 5555555555555555 (hex) for all devices for CYNSE10512. CFG[31:0] = 55555555 (hex) for all devices for CYNSE10256, and CFG[15:0] = 5555 (hex) for all devices for CYNSE10128. For Enhanced Mode, NES in each block for all devices should be set to “01” to create 144-bit table. ...
Page 73
... BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] Block of 8 Ayama 10000s Block 2 (Devices 16–23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] Block of 7 Ayama 10000s Block 3 (Devices 24–30) BHO[2] BHO[1] BHO[0] CYNSE10512 CYNSE10256 CYNSE10128 SRAM GND GND GND Page 73 of 153 [+] Feedback [+] Feedback ...
Page 74
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 75
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 76
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0] stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI(6:0) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 77
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 78
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 79
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 80
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 81
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 82
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 83
... GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 by this device if it has a hit. CMD[9] must be driven to logic high to indicate a 144-bit search. ...
Page 84
... L will be driven as part of the SRAM address on the SADR[N:0] lines (see “SRAM PIO Access” on page 121 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. The global winning device will drive the bus in a specific cycle. On global miss cycles, the device with LRAM = 1 (binary) and LDEV = 1 (binary) will be the default driver for such missed cycles ...
Page 85
... Figure 6-33 shows the same for device number 1 and number 7 (the last device in this specific table) respectively. Table 6-9. Hit/Miss Assumptions Search Number Device 0 Device 1 Devices 2–6 Device 7 Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY 1 2 Hit Miss Miss Hit Miss Miss Miss Miss CYNSE10512 CYNSE10256 CYNSE10128 3 Miss Miss Miss Miss Page 85 of 153 [+] Feedback [+] Feedback ...
Page 86
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 6-31. Timing Diagram for 576-bit Single Search Device Number 0 Document #: 38-02069 Rev ...
Page 87
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 6-32. Timing Diagram for 576-bit Single Search Device Number 1 Document #: 38-02069 Rev ...
Page 88
... SSV 0 SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 6-33. Timing Diagram for 576-bit Single Search Device Number 7 (Last Device) The following is the sequence of operation for a single 576-bit Search command (also refer to Subsection 6.2, “ ...
Page 89
... L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. The global winning device will drive the bus in a specific cycle global miss cycle, the device with LRAM = 1 (binary) (default driving device for the SRAM bus) and LDEV = 1 (binary) (default driving device for SSF and SSV signals) will be the default driver for such missed cycles ...
Page 90
... Devices 2–6 Miss Device 7 Miss Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY 2 Hit Miss Miss Miss Hit Miss Miss Miss Miss Miss Miss Hit CYNSE10512 CYNSE10256 CYNSE10128 , which is either DDQ_ASIC 3 Miss Miss Miss Miss Miss Miss Miss Miss Page 90 of 153 [+] Feedback [+] Feedback ...
Page 91
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ of the entire LHI bus. Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal. ...
Page 92
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ of the entire LHI bus. Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal. ...
Page 93
... SSV 0 SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ of the entire LHI bus. Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal. ...
Page 94
... SADR[24:23] for CYNSE10512, SADR[23:22] for CYNSE10256, SADR[22:21] for CYNSE10128 by this device if it has a hit. CMD[8] must be driven HIGH for every A-cycle. CMD[9] is don’t care for this cycle. — DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with 72-bit data (which is part of the 576-bit data compared. • ...
Page 95
... AAAAAAAAAAAAAAAA (hex) for CYNSE10512, CFG[31:0] = AAAAAAAA (hex) for CYNSE10256, CFG[15:0] = AAAA (hex) for CYNSE10128 for Non-Enhanced Mode, NES = “10” (binary) in all blocks for Enhanced Mode). The following figures show three sequential searches: first, a 72-bit Search on a ×72-configured table; a 144-bit Search on a ×144-configured table; and a 288-bit Search on a × ...
Page 96
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode, CFG = all zeroes NES = 00 (binary) in all blocks for Enhanced Mode, x72 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-40. Timing Diagram for Mixed Search for Devices Above Block 0 Winning Device Document #: 38-02069 Rev ...
Page 97
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CFG = all zeroes for Non-Enhanced Mode NES = 00 (binary) in all blocks for Enhanced Mode, x72 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-41. Timing Diagram for Mixed Search for Block 0 Winning Device Document #: 38-02069 Rev ...
Page 98
... SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CFG = all zeroes for Non-Enhanced Mode NES = 00 (binary) in all blocks for Enhanced Mode, x72 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0, LDEV = 0 (binary). Figure 6-42. Timing Diagram for Mixed Search for Devices Below Block 0 Winning Device Document #: 38-02069 Rev ...
Page 99
... WE_L z OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = 5555555555555555h; CYNSE10256: CFG[31:0] = 55555555h; CYNSE10128: CFG[15:0] = 5555h. NES = 01 (binary) in all blocks for Enhanced Mode, x144 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 100
... WE_L z OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = 5555555555555555h; CYNSE10256: CFG[31:0] = 55555555h; CYNSE10128, CFG[15:0] = 5555h. NES = 01 (binary) in all blocks for Enhanced Mode, x144 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 101
... WE_L z OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = 5555555555555555h; CYNSE10256: CFG[31:0] = 55555555h; CYNSE10128, CFG[15:0] = 5555h. NES = 01 (binary) in all blocks for Enhanced Mode, x144 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 102
... WE_L z OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256: CFG[31:0] = AAAAAAAAh; CYNSE10128, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 103
... WE_L z OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256: CFG[31:0] = AAAAAAAAh; CYNSE10128, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 104
... WE_L z OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256: CFG[31:0] = AAAAAAAAh; CYNSE10128, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search. HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 105
... WE_L z OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256: CFG[31:0] = AAAAAAAAh; CYNSE10128, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search. HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 106
... OE_L 0 SSV 0 SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 For Non-Enhanced Mode: CYNSE10512: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256: CFG[31:0] = AAAAAAAAh; CYNSE10128, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 1 (binary), LDEV = 1 (binary). ...
Page 107
... L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. Note. The Learn command is supported for only one of the blocks consisting eight devices in a depth-cascaded table of more than one block ...
Page 108
... Miss Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY #2 (x144) Hit Miss Miss Hit Miss Miss Miss Miss Hit Miss Miss Miss Miss Miss Miss CYNSE10512 CYNSE10256 CYNSE10128 #3 (x288) Miss Miss Miss Miss Miss Miss Miss Miss Hit Miss Page 108 of 153 [+] Feedback [+] Feedback ...
Page 109
... OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 NES = 00 (binary) in all blocks for Enhanced Mode, x72 search. HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-52. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 0 Document #: 38-02069 Rev. *F ...
Page 110
... OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 NES = 00 (binary) in all blocks for Enhanced Mode, x72 search. HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-53. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 1 Document #: 38-02069 Rev. *F ...
Page 111
... OE_L z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 NES = 01 (binary) in all blocks for Enhanced Mode, x144 search. HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-54. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 2 Document #: 38-02069 Rev. *F ...
Page 112
... OE_L 0 SSV 0 SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 NES =10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-55. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 7 Document #: 38-02069 Rev. *F ...
Page 113
... La and Lb will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. Note. The Learn command is supported for only one of the blocks consisting eight devices in a depth-cascaded table of more than one block ...
Page 114
... Learn Learn Learn Mask Learn from CMPR CMPR CMPR a b x72 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle Page 114 of 153 [+] Feedback [+] Feedback ...
Page 115
... Learn 288-bit Learn Learn Mask Learn from CMPR CMPR CMPR CMPR CMPR for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle Page 115 of 153 [+] Feedback [+] Feedback ...
Page 116
... Learn CMPR CMPR CMPR CMPR for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle Page 116 of 153 [+] Feedback [+] Feedback ...
Page 117
... PRELIMINARY cycle cycle cycle cycle cycle cycle cycle cycle 576-bit Learn CMPR CMPR CMPR CMPR for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle Page 117 of 153 [+] Feedback [+] Feedback ...
Page 118
... X Learn1 X Learn2 Comp2 Comp1 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle cycle Page 118 of 153 [+] Feedback [+] Feedback ...
Page 119
... Learn2 X Learn1 X Comp2 Comp1 X X 1A1B for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle cycle Page 119 of 153 [+] Feedback [+] Feedback ...
Page 120
... For a Learn in a 72-bit-configured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven on SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 in the SRAM Write cycle. ...
Page 121
... Cycle 5: The selected device drives the Read address on SADR[N:0] lines ( for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128) and drives ACK HIGH, CE_L LOW, and ALE_L LOW. • Cycle 6: The selected device drives CE_L HIGH, ALE_L HIGH, the SADR bus, the DQ bus in a three-state condition, and ACK LOW ...
Page 122
... Cycle 6: The selected device drives the Read address on SADR[N:0] lines ( for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128) and drives ACK HIGH, CE_L LOW, WE_L HIGH, and ALE_L LOW. • Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and the DQ bus in a three-state condition. It continues to drive ACK LOW ...
Page 123
... LHI Ayama 10000 #5 LHO[ LHI LHI Ayama 10000 #6 LHO[ LHI LHI Ayama 10000 #7 LHO[1] LHO[0] CYNSE10512 CYNSE10256 CYNSE10128 SRAM LHO[ LHO[ LHO[ BHO[0] BHO[0] BHO[1] BHO[1] BHO[2] BHO[2] Page 123 of 153 ...
Page 124
... Figure 6-65. SRAM Read of Device # Block of Eight Devices Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY cycle cycle cycle cycle driven by selected Ayama 10000 , LRAM = 0 , LDEV = 0 (binary) (binary) (binary) CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle Address 1 0 Page 124 of 153 [+] Feedback [+] Feedback ...
Page 125
... DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6]. • Cycle 1B: The host ASIC continues to apply the Read instruction to CMD[1:0], using CMDV = 1. The DQ bus supplies the address, with DQ[20:19] set to 10, to select the SRAM address. • ...
Page 126
... ALE_L z SADR[M:0] z ACK z SSV z SSF for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 TLSZ = 10 (binary), HLAT = 010 (binary), LRAM = 0 (binary), LDEV = 0 (binary) Figure 6-68. SRAM Read of Device # Bank of 31 Devices Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY BHI[2] BHI[1] BHI[0] Block of 8 Ayama 10000s Block 0 (devices 0– ...
Page 127
... DQ[20:19] set select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported. ...
Page 128
... TLSZ = 00 (binary), HLAT = 000 (binary), LRAM = 1 (binary), LDEV = 1 (binary) Figure 6-70. SRAM Write Access (TLSZ = 00 (binary), HLAT = 000 (binary), LRAM = 1 (binary), LDEV = 1 (binary)) Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY cycle cycle cycle cycle Write Address CYNSE10512 CYNSE10256 CYNSE10128 cycle Address Page 128 of 153 [+] Feedback [+] Feedback ...
Page 129
... DQ[20:19] set select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported. ...
Page 130
... ALE_L z SADR[M: ACK z SSV z SSF TLSZ = 01 (binary), HLAT = XXX, LRAM = 0 (binary), LDEV = 0 (binary for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 Figure 6-72. SRAM Write of Device # Block of Eight Devices Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY cycle cycle cycle cycle cycle cycle cycle ...
Page 131
... DQ[20:19] set select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported. ...
Page 132
... SADR[M:0] z ACK z SSV z SSF TLSZ = 10 (binary), HLAT = XXX, LRAM = 0 (binary), LDEV = 0 (binary for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 Figure 6-75. SRAM Write of Device #0 in Bank of 31 Devices Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY BHI[2] BHI[1] BHI[0] Block of 8 Ayama 10000s Block 0 (devices 0–7) ...
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... SSV 0 SSF TLSZ = 10 (binary), HLAT = XXX, LRAM = 1 (binary), LDEV = 1 (binary for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128 Figure 6-76. SRAM Write Through Device #30 in Bank of 31 Devices 6.8 Timing Sequences for Back-to-Back Operations Table 6-14 shows the idle cycle requirements between operations. The operations in the second column represent operations already performed, and the operations in the first row are those we would like to perform next ...
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... Search3 Search5 x144 Search2 Search4 Searches 1 and 2 shows Search 3 shows x144 x72 table full table not full CYNSE10512 CYNSE10256 CYNSE10128 cycle cycle cycle cycle M-Search3 tables 0 1 are not full ...
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... Description Revision Number. This is the current device revision number. Numbers start from one and increment by one for each revision of the device. Part Number. This is the part number for CYNSE10128. This is the part number for CYNSE10256. This is the part number for CYNSE10512. ...
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... Figure 8-1. Typical Power Consumption of Ayama 10000 Note: These values were determined through our power estimation model. Please contact Cypress to get an application specific power estimation. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY 50 83 Operating Frequency (MHz) Ayama10256 CYNSE10512 CYNSE10256 CYNSE10128 100 133 Ayama10128 Page 136 of 153 [+] Feedback [+] Feedback ...
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... DDQ 0.1 0 Min., 0.4 DDQ DDQ = Min., V – DDQ DDQ DDQ = 2 mA 0.4 Description Min. Typ. 2.3 1.65 1.4 0.68 0.75 1.14 0 –40 30pF, and all others 6pF REF CYNSE10512 CYNSE10256 CYNSE10128 2.5V DDQ DDQ Min. Max. Min. Max. Unit –10 10 –10 10 –10 10 –10 10 -0.3 0.35 –0.3 0.7 V DDQ 0. 1 DDQ DDQ V 0 ...
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... Min. 100 166 100 0.5 2.4 2.0 2.4 2.0 [23] 1.8 1.5 [23] 0.6 0.5 4.5 4 1.8 1 0.8 0.7 [27, 3.9 7 0.75 0.75 1.2 1.2 3.2 7 0.75 0.75 1.2 1.2 [26] 3.5 [26, 30] 0.5 1.8 0.5 [26] 3.5 [26, 30] 0.5 1.8 0.5 [26, 30] 2.2 1.9 0.5 0.5 100 100 CYNSE10512 CYNSE10256 CYNSE10128 Ayama 10000- 133 Max. Min. Max. Unit 200 100 266 MHz 0.5 0.5 ms 1.5 ns 1.5 ns 1.0 ns 0 0.5 ns 3.4 2 2 3.0 2.5 ns 1.8 0.5 1 ...
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... Signal Group 5: DQ, ACK, EOT, PAR, MULTI_HIT, FULL (Enhanced mode) Figure 10-1. AC Timing Wave Forms with CLK2X Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY t IHCH t ISCH t CKHOV* t CKHOV* t CKHSHZ t CKHSLZ t CKHSV t CKHSHZ CKHSLZ t CKHSV t CKHSV t t CKHDV, CKHOVFE CYNSE10512 CYNSE10256 CYNSE10128 t CKHDZ Page 139 of 153 [+] Feedback [+] Feedback ...
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... Max. Min 0.5 [23] 5.4 4.5 [23] 5.4 4.5 [23] 1.8 1.5 [23] 0.6 0.5 4.5 1.8 1.5 [24, 0 0.8 0.7 [27, 28] 3.9 7 0.75 0.75 1.2 1.2 3.2 7 0.75 0.75 1.2 1.2 [24] 3.5 [28] 0.5 1.8 0.5 [24] 3.5 [28] 0.5 1.8 0.5 [28] 1.9 1.9 0.5 0.5 100 100 CYNSE10512 CYNSE10256 CYNSE10128 Ayama 10000- 100 133 Max. Min. Max. Unit 100 50 133 MHz 0.5 0.5 ms 3.4 ns 3.4 ns 1 0.5 ns 3.4 2 2 3.0 2.5 ns 1.8 0.5 1 ...
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... CONFIDENTIAL PRELIMINARY Ayama 10000- Ayama 10000- 083 100 Min. Max. Min. 10 100 100 CYNSE10512 CYNSE10256 CYNSE10128 Ayama 10000- 133 Max. Min. Max. Unit 10 10 MHz 100 ...
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... Signal Group 5: DQ, ACK, EOT, MULTI_HIT, PAR, FULL (Enhanced) Figure 10-2. AC Timing Wave Forms with CLK1X Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY t IHCH t IHCH ICHCH* t CKHOV* t CKHOV* t CKHSHZ t CKHSHZ CKHSLZ t CKHSV t t CKHSV t t CKHDV, CKHOVFE CYNSE10512 CYNSE10256 CYNSE10128 CKHDZ Page 142 of 153 [+] Feedback [+] Feedback ...
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... GND Figure 10-3. LVCMOS I/O Input Waveform 50 Ω 1 OUT L 6pF V = 2.5V DDQ 479 Ω D For high-Z OUT 6 pF 523 Ω 1.8V DDQ 470 Ω D For high-Z OUT 6 pF 470 Ω CYNSE10512 CYNSE10256 CYNSE10128 Results DDQ Page 143 of 153 [+] Feedback [+] Feedback ...
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... Faster than 1 V/ns (see Figure 10-7) 0.75V 0.75V +1.25V 80% 80% 20% 20% 0.25V Figure 10-7. HSTL I/II I/O Input Waveform 50 Ω 1 OUT L 6pF 25 Ω 1 OUT L 6pF V = 1.5V DDQ 479 Ω D For high-Z OUT 6 pF 523 Ω CYNSE10512 CYNSE10256 CYNSE10128 Results DDQ DDQ Page 144 of 153 [+] Feedback [+] Feedback ...
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... CLK DR DDQ_S Figure 11-1. Pinout Diagram (Top View) CYNSE10512 CYNSE10256 CYNSE10128 LHI [ 2 ] LHI [ ...
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... AC3 GND AE10 GND AE11 GND AE12 GND AE13 GND AE14 GND AE15 INPUT AE16 I/O AE17 1.2V AE18 1.2V AE19 1.2V AE2 1.2V AE20 CYNSE10512 CYNSE10256 CYNSE10128 Signal Name Signal Type CMD[2] INPUT V 1. GND SS FULL OUTPUT-T ACK OUTPUT-T V GND SS V 1.2V DD CMD[5] INPUT CMD[4] INPUT V 1.2V ...
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... AF16 I/O B23 I/O B24 1.5V/1.8V/2.5V B25 NO CONNECT B26 I/O B3 I/O B4 I/O B5 OUTPUT-T B6 OUTPUT-T B7 INPUT B8 INPUT B9 I/O C1 I/O C10 I/O C11 1.5V/1.8V/2.5V C12 I/O C13 I/O C14 I/O C15 INPUT C16 I/O C17 I/O C18 1.5V/1.8V/2.5V C19 CYNSE10512 CYNSE10256 CYNSE10128 Signal Name Signal Type DQ[06] I/O V 1.5V/1.8V/2.5V DDQ_ASIC DQ[00] I/O V 1.5V/1.8V/2.5V DDQ_ASIC V GND CONNECT DQ[70] I/O V 1.5V/1.8V/2.5V DDQ_ASIC DQ[64] I/O DQ[60] I/O DQ[58] I/O DQ[54] I/O DQ[50] I CONNECT V 1.5V/1.8V2.5V DDQ_ASIC DQ[40] I/O DQ[36] I/O DQ[34] I/O DQ[30] I/O V 1.5V/1.8V2.5V ...
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... G24 INPUT G25 GND G26 GND G3 1.2V G4 OUTPUT-T H1 OUTPUT-T H2 1.2V H23 GND H24 GND H25 GND H26 GND H3 GND H4 GND J1 INPUT J2 2.5V J23 CYNSE10512 CYNSE10256 CYNSE10128 Signal Name Signal Type TMS INPUT 1.2V DD SADR[1] OUTPUT-T V 1.5V/1.8V/2.5V DDQ_SRAM ...
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... GND P2 GND P23 GND P24 GND P25 GND P26 1.2V U24 1.2V U25 1.5V/1.8V/2.5V U26 GND U3 GND U4 GND V1 GND V2 GND V23 GND V24 CYNSE10512 CYNSE10256 CYNSE10128 Signal Name Signal Type SADR[11] OUTPUT-T BHI[0] INPUT 1.5V/1.8V/2.5V DDQ_SRAM SADR[17] OUTPUT 1.2V DD BHI[1] INPUT V GND SS V ...
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... V DD T24 V DD_PLL T25 CLK_MODE T26 SADR[23 FULI[ DDQ_ASIC U23 V SS_PLL Notes: 31. No-Connect in CYNSE10256 and CYNSE10128. 32. No-Connect in CYNSE10256. Document #: 38-02069 Rev. *F CONFIDENTIAL PRELIMINARY Package Ball Signal Type Number OUTPUT-T V25 1.2V V26 1.2V V3 OUTPUT-T V4 1.5V/1.8V/2.5V W1 1.2V W2 1.2V W23 OUTPUT-T W24 GND ...
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... Cypress against all charges. CONFIDENTIAL PRELIMINARY 388-Ball HFC-BGA FG388A 3.32 MAX B 0.15(4X) Description I/O Voltage 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V 1.5V/1.8V/2.5V CYNSE10512 CYNSE10256 CYNSE10128 Ø0. Ø0. Ø0.75±0.05(388X) A1 CORNER ...
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... Document History Page Document Title: CYNSE10512/CYNSE10256/CYNSE10128 Ayama 10000 Network Search Engine Document Number: 38-02069 ECN Issue Orig. of REV. NO. Date Change ** 119954 01/16/03 BGT New Data Sheet *A 123910 02/13/03 KHS for Added the following information: ITL 32 CLK2X cycles wait after a write to COMMAND register Enhanced mode Block configuration (in BMR) prior to entries initialization ...
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... Document Title: CYNSE10512/CYNSE10256/CYNSE10128 Ayama 10000 Network Search Engine Document Number: 38-02069 ECN Issue Orig. of REV. NO. Date Change *E 212292 See KHS p10: 576-bit configuration is supported in Enhanced Mode only ECN p15-p17, Table 4-1: General signal description clarification p27, Figure 5-9: Added addresses value of the GMR Registers ...