CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 16

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 4-1. Ayama™ 10000 Signal Description (continued)
Document #: 38-02069 Rev. *F
CMDV
DQ[71:0]
PAR[1:0]
ACK
EOT
SSF
SSV
MULTI_HIT
FULL
HIGH_SPEED1
HIGH_SPEED2
SRAM Interface (LVCMOS or HSTL I/II)
SADR[M:0]
CE_L
WE_L
OE_L
ALE_L
[5]
[5]
[4]
[4]
[5]
[5]
[5]
[5]
Parameter
[5]
[5]
Type
I/O
I/O
O
T
T
T
T
T
T
T
T
T
T
I
I
I
[2]
Command Valid. This signal indicates valid command in the CMD bus when set to High.
Address/Data Bus. This signal carries the following information:
Search operation: Compare Data (Search Key)
SRAM PIO operations: SRAM Address
Other operations to Register, Data, and Mask Array regions: Address and Data
Parity Bus. These signals contain the even parity values for the DQ bus. On the Read
return data, the NSE generates the parity bits. On all other operations these bits are
externally driven. Bit [0] is the parity for all even DQ signals. Bit[1] is the parity for all odd
DQ signals.
Read Acknowledge. This signal indicates that valid data is available on the DQ bus
during register, data, and mask array Read operations, or that the data is available on the
SRAM data bus during SRAM Read operations.
End of Transfer. This signal indicates the end of burst transfer to the data or mask array
during Read or Write burst operations.
Search Successful Flag. When asserted, this signal indicates that the device is the
global winner in a Search operation.
Search Successful Flag Valid. When asserted, it indicates valid SSF value. In Enhanced
mode, this signal also indicates valid FULL and MULTI_HIT values.
Multiple Hit Flag. In a Search operation, this signal indicates that there are multiple
entries in the array or in the selected blocks that match the Search key when it is set to
1. In a Learn operation, it indicates that there are multiple free entries.
In Non-Enhanced mode, it becomes valid 4 CLK1X cycles after the command is issued.
In Enhanced mode, it becomes valid when SSV is 1.
Full Flag. When High, it indicates that the table in the array or in the selected blocks
(Enhanced mode) is full.
In the Non-Enhanced mode, it becomes valid 4 CLK1X cycles after the command is
issued.
In the Enhanced mode, it becomes valid when SSV is 1.
High Speed 1. This signal must be pulled High (V
at CLK2X frequency above 166 MHz.
High Speed 2. This signal must be pulled High (V
at CLK2X frequency above 200 MHz.
SRAM Address. This bus contains address lines to access off-chip SRAMs that contain
associative data. In a cascaded system of multiple Ayama 10000 NSEs, each corre-
sponding SADR bit from all cascaded devices must be tied together.
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128.
SRAM Chip Enable. This is the chip enable (CE) control for external SRAMs. In a
cascaded system of multiple Ayama 10000 NSEs, CE_L of all cascaded devices must be
tied together. This signal is then driven by only one of the devices.
SRAM Write Enable. This is the Write enable control for external SRAMs. In a cascaded
system of multiple Ayama 10000 NSEs, WE_L of all cascaded devices must be tied
together. This signal is then driven by only one of the devices.
SRAM Output Enable. This is the output enable (OE) control for external SRAMs. Only
the last device drives this signal (the device that has the LRAM bit set).
Address Latch Enable. When this signal is Low, the addresses are valid on the SRAM
address bus. In a cascaded system of multiple Ayama 10000s, the ALE_L of all cascaded
devices must be tied together. This signal is then driven by only one of the devices.
CONFIDENTIAL
PRELIMINARY
Description
DDQ_ASIC
DDQ_ASIC
) when the device operates
) when the device operates
CYNSE10512
CYNSE10256
CYNSE10128
Page 16 of 153
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