ST62E80B STMICROELECTRONICS [STMicroelectronics], ST62E80B Datasheet - Page 24

• Manufacturer Part Number: ST62E80B
• Description: 8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST62T80B/E80B
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 . This register is set to 0FEh on Re-
set: bit C is cleared to “0”, which disables the
Watchdog; the timer downcounter bits, T0 to T5,
and the SR bit are all set to “1”, thus selecting the
longest Watchdog timer period. This time period
can be set to the user’s requirements by setting
the appropriate value for bits T0 to T5 in the
DWDR register. The SR bit must be set to “1”,
since it is this bit which generates the Reset signal
when it changes to “0”; clearing this bit would gen-
erate an immediate Reset.
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated in Figure 14.
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384 s to 24.576ms).
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Figure 14. Watchdog Counter Control
D0
D1
D2
D3
D4
D5
D6
D7
2
8
SR
T5
T4
T3
T2
T1
T0
C
OSC 12
RESET
VR02068A