ST62E80B STMICROELECTRONICS [STMicroelectronics], ST62E80B Datasheet - Page 50

no-image

ST62E80B

Manufacturer Part Number
ST62E80B
Description
8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
ST62T80B/E80B
4.4.2 CLOCK GENERATION
The UART contains a built-in divider of the MCU
internal clock for most common Baud Rates as
shown in Table 18. Other baud rate values can be
calculated from the chosen oscillator frequency di-
vided by the Divisor value shown.
The divided clock provides a frequency that is 8
times the desired baud rate. This allows the Data
reception mechanism to provide a 2 to 1 majority
voting system to determine the logic state of the
asynchronous incoming serial logic bit by taking 3
timed samples within the 8 time states.
The bits not sampled provide a buffer to compen-
sate for frequency offsets between sender and re-
ceiver.
4.4.3 DATA TRANSMISSION
Transmission is fixed to a format of one start bit,
nine data bits and one stop bit. The start and stop
bits are automatically generated by the UART. The
nine databits are under control of the user and are
flexible in use. Bits 0..7 are typically used as data
bits while bit 9 is typically used as parity, but can
also be a 9th data bit or an additional Stop bit. As
parity is not generated by the UART, it should be
calculated by program and inserted in the appro-
priate position of the data (i.e as bit 7 for 7-bit data,
with Bit 9 set to 1 giving two effective stop bits or
as the independent bit 9).
Figure 26. Data Sampling Points
50/78
50
0
1
2
3
SAMPLES
1 BIT
4
5
6
7
VR02010
8
The character options are summarised in the fol-
lowing table.
Table 17. Character Options
Bit 9 remains in the state programmed for consec-
utive transmissions until changed by the user or
until a character is received when the state of this
bit is changed to that of the incoming bit 9. The
recommended procedure is thus to set the value of
this bit before transmission is started.
Transmission is started by writing to the Data Reg-
ister (the Baud Rate and Bit 9 should be set before
this action). The UARTOE signal switches the out-
put multiplexer to the UART output and a start bit
is sent (a 0 for one bit time) followed by the 8 data
values (lsb first) and the value of the Bit9 bit. The
output is then set to 1 for a period of one bit time to
generate a Stop bit, and then the UARTOE signal
returns the TXD1 line to its alternate I/O function.
The end of transmission is flagged by setting
TXMT to 1 and an interrupt is generated if ena-
bled. The TXMT flag is reset by writing a 0 to the
bit position, it is also cleared automatically when a
new character is written to the Data Register.
TXMT can be set to 1 by software to generate a
software interrupt so care must be taken in manip-
ulating the Control Register.
Figure 27. Character Format
Start Bit
Start Bit
Start Bit
Start Bit
POSITION
BIT
START
START OF DATA
BIT
8 Data
9 Data
8 Data
7 Data
D0 D1
1
2
1 Software Parity
No Parity
No Parity
1 Software Parity
D7 D8
8
9
10
CHARACTER
STOP
BIT
POSSIBLE
START
NEXT
VR02012
1 Stop
1 Stop
2 Stop
2 Stop

Related parts for ST62E80B