AS1419A AUSTIN [Austin Semiconductor], AS1419A Datasheet
AS1419A
Related parts for AS1419A
AS1419A Summary of contents
Page 1
... The ADC has a microprocessor compatible, 14-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and data ready signal (BUSY\) ease connections to FIFOs, DSPs and microprocessors. AS1419 & AS1419A Rev. 1.5 08/09 MARKING F ECA o ...
Page 2
... Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio AS1419 & AS1419A Rev. 1.5 08/09 * *Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those - 0 ...
Page 3
... High Level Output Voltage Low Level Output Voltage High-Z Output Leakage D13 to D0 High-Z Output Capacitance D13 to D0 Output Source Current Output Sink Current AS1419 & AS1419A Rev. 1.5 08/09 (* denotes specifications which apply over the full CONDITIONS 100kHz Input Signal 390 kHz Input Signal ...
Page 4
... Data Ready Before BUSY\ 10 Delay Between Conversions 9 Wait Time RD\ After BUSY\ Data Access Time After RD\ Bus Relinquish Time RD\ Low Time CONVST\ High Time AS1419 & AS1419A Rev. 1.5 08/09 (* denotes specifications which apply over the full CONDITIONS (* denotes specifications which apply over the * * * * * ...
Page 5
... A grounded FUNCTIONAL BLOCK DIAGRAM AS1419 & AS1419A Rev. 1.5 08/09 7. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 8. Bipolar offset is the offset voltage measured from –0.5LSB ...
Page 6
... Austin Semiconductor, Inc. TYPICAL PERFORMANCE CHARACTERISTICS AS1419 & AS1419A Rev. 1.5 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 ADC ADC ADC ADC ADC AS1419 AS1419A ...
Page 7
... Shutdown mode selected by CS\. CS for nap mode and CS for sleep mode. RD\ (Pin 22): Read Input. This enables the output drivers when CS\ is low. AS1419 & AS1419A Rev. 1.5 08/09 Load Circuits for Output Float Delay CONVST\ (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge ...
Page 8
... IN IN contents (a 14-bit data word) which represents the difference of +AIN and –AIN are loaded into the 14-bit output latches. AS1419 & AS1419A Rev. 1.5 08/09 DYNAMIC PERFORMANCE The AS1419 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’ ...
Page 9
... AS1419 maintains near ideal ENOBs up to the Nyquist input frequency of 400kHz (refer to Figure 3). FIGURE 3: Effective Bits and Signal/ (Noise+Distortion) vs. Input Frequency AS1419 & AS1419A Rev. 1.5 08/09 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself ...
Page 10
... During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, AS1419 & AS1419A Rev. 1.5 08/09 then the AS1419 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time with high source impedance, a buffer amplifier should be used ...
Page 11
... The filtering of the internal AS1419 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment. AS1419 & AS1419A Rev. 1.5 08/09 FIGURE 8a: FIGURE 8b: pin by 1.625 to create the FIGURE 9: Austin Semiconductor, Inc ...
Page 12
... Figure 10b shows a circuit that converts analog input signal with only an additional buffer that is not in the signal path. AS1419 & AS1419A Rev. 1.5 08/09 Full-Scale and Offset Adjustment Figure 11a shows the ideal input/output characteristics for the AS1419. The code transitions occur midway between successive integer LSB values (i.e., – ...
Page 13
... CMRR. The –A a ground sense for the +A input; the AS1419 will hold and IN convert the difference voltage between +A FIGURE 12: Power Supply Grounding Practice AS1419 & AS1419A Rev. 1.5 08/09 leads to +A possible. In applications where this is not possible, the +A and –A IN coupling ...
Page 14
... The falling edge of CONVST\ starts the FIGURE 14a: CS\ to SHDN\ Timing FIGURE 15: CS\ to CONVST\ Set-Up Timing AS1419 & AS1419A Rev. 1.5 08/09 conversion. The data outputs are always enabled and data can be latched with the BUSY\ rising edge. Mode 1a shows operation with a narrow logic low CONVST\ pulse ...
Page 15
... Austin Semiconductor, Inc. FIGURE 16: Mode 1a. CONVST\ Starts a Conversion. Data Outputs Always Enabled. (CONVST\ = AS1419 & AS1419A Rev. 1.5 08/09 ) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 ADC ADC ADC ADC ADC AS1419 AS1419A ...
Page 16
... Austin Semiconductor, Inc. AS1419 & AS1419A Rev. 1.5 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 ADC ADC ADC ADC ADC AS1419 AS1419A ...
Page 17
... Austin Semiconductor, Inc. *All measurements are in inches. AS1419 & AS1419A Rev. 1.5 08/09 MECHANICAL DEFINITIONS* 28-Pin Flat Pack (Package Designator F) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 AS1419 AS1419A + - + - .330 0.006 .410 0.005 ADC ADC ADC ADC ADC ...
Page 18
... Austin Semiconductor, Inc. *All measurements are in inches. AS1419 & AS1419A Rev. 1.5 08/09 MECHANICAL DEFINITIONS* 28-Pin LCC Package (Package Designator ECA) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 ADC ADC ADC ADC ADC AS1419 AS1419A ...
Page 19
... Austin Semiconductor, Inc. *AVAILABLE PROCESSES XT = Extended Temperature Range IT = Industrial Temperature Range MIL = Military Processing SPACE = Space Processing** *As defined by individual customer Source Control Drawing (SCD) AS1419 & AS1419A Rev. 1.5 08/09 ORDERING INFORMATION EXAMPLE: AS1419F-SPACE Package Operating Device Number Type AS1419 F AS1419A F EXAMPLE: AS1419AECA-883C ...
Page 20
... Changed text Changed power requirement 1.5 1.3 Updated drawing Specifications 1.4 Updated Timing Characteristics 1.5 Added SCD note under Space Option Page 1 & 19 AS1419 & AS1419A Rev. 1.5 08/09 Release Date 2/05 5/05 7/08 8/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 ADC ADC ...