LTC1279 LINER [Linear Technology], LTC1279 Datasheet - Page 8

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LTC1279

Manufacturer Part Number
LTC1279
Description
12-Bit, 600ksps Sampling A/D Converter with Shutdown
Manufacturer
LINER [Linear Technology]
Datasheet

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TI I G DIAGRA S
APPLICATIONS
CONVERSION DETAILS
The LTC1279 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
capacitor during the acquire phase, and the comparator
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 160ns will provide enough
LTC1279
TEST CIRCUITS
8
RD
CS
W U
DBN
CS to RD Setup Timing
t
A) HIGH-Z TO V
1
AND V
3k
Load Circuits for Access Timing
DGND
IN
OL
input connects to the sample-and-hold
TO V
OH
U
OH
(t
8
(t
)
6
C
)
INFORMATION
L
1279 TD01
U
W
DBN
W
B) HIGH-Z TO V
AND V
CONVST
OH
5V
CS to CONVST Setup Timing
CS
TO V
3k
DGND
U
C
OL
L
OL
1279 TC01
(t
8
(t
)
6
)
t
2
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches C
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
A
DBN
IN
SAMPLE
1279 TD02
HOLD
A) V
Load Circuits for Output Float Delay
3k
OH
DGND
C
TO HIGH-Z
SAMPLE
C
V
DAC
DAC
Figure 1. A
CONVST
SHDN to CONVST Wake-Up Timing
10pF
DAC
SHDN
IN
Input
SAMPLE
+
COMPAR-
DBN
ATOR
SI
t
3
B) V
OL
TO HIGH-Z
5V
12-BIT
LATCH
1279 F01
SAMPLE
3k
DGND
R
S
A
10pF
1279 TC02
1279 TD03
to

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