MG2 ATMEL [ATMEL Corporation], MG2 Datasheet

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MG2

Manufacturer Part Number
MG2
Description
350K Used Gates 0.5 ?m CMOS Sea of Gates
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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Features
Description
The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up
to 480K gates cover most system integration needs. The MG2 is manufactured using
a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2.
The base cell architecture of the MG2 series provides high routability of logic with
extremely dense compiled memories: RAM and DPRAM. ROM can be generated
using synthesis tools.
Accurate control of clock distribution can be achieved by PLL hardware and CTS
(Clock Tree Synthesis) software. New noise prevention techniques are applied in the
array and in the periphery: three or more independent supplies, internal decoupling,
customization dependent supply routing, noise filtering, skew controlled I/Os, low
swing differential I/Os, all contribute to improve the noise immunity and reduce the
emission level.
The MG2 is supported by an advanced software environment based on industry stan-
dards linking proprietary and commercial tools. Verilog, Modelsim, Design Compiler
are the reference front-end tools. Floor planning associated with timing driven layout
provides a short back-end cycle.
The MG2 library allows straight forward migration from MG1 Sea of Gates. A netlist
based on this library can be simulated as either MG2, or MG2RT or MG2RTP.
Full Range of Matrices with up to 480K Gates
0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM and DPRAM Compilers
Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
3 and 5 Volts Operation; Single or Dual Supply Mode
High Speed Performances
Programmable PLL Available on Request
High System Frequency Skew Control through Clock Tree Synthesis Software
Low Power Consumption:
Integrated Power On Reset
Matrices With a Max of 484 Fully Programmable Pads
Standard 3, 6, 12 and 24 mA I/Os
Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 KV) and Latch-up Protected I/O
High Noise and EMC Immunity:
Wide Range of Hermetic and Plastic Packages
Delivery in Die Form with 94.6 µm Pad Pitch
Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,
Power Management
Cadence
EDIF and VHDL Reference Formats
Available In Commercial, Industrial and Military Quality Grades (for Space Application
see MG2RT and MG2RTP Specifications)
QML Q with SMD 5962-00B02
– 420 ps Max NAND2 Propagation Delay at 4.5V, 670 ps at 2.7 and FO = 5
– Min 650 MHz Toggle Frequency at 4.5V and 340 MHz at 2.7V
– 1.96 µW/Gate/MHz at 5V
– 0.6 µW/Gate/MHz at 3V
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery and Core
– Application Dependent Supply Routing and Several Independent Supply Sources
®
, Mentor
, Vital and Synopsys
®
Reference Platforms
350K Used Gates
0.5 µm CMOS
Sea of Gates
MG2
4137O–AERO–06/05

Related parts for MG2

MG2 Summary of contents

Page 1

... QML Q with SMD 5962-00B02 Description The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up to 480K gates cover most system integration needs. The MG2 is manufactured using a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2. The base cell architecture of the MG2 series provides high routability of logic with extremely dense compiled memories: RAM and DPRAM ...

Page 2

... Table 1. List of Available MG2 Matrices Note: Libraries The MG2 cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available in VHDL, for example: I2C, UART, Timer, etc ...

Page 3

... For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms. PLL Contact factory. 4137O–AERO–06/05 Frequency (MHz) Oscillators Max 5V Xtal 7M 12 Xtal 20M 28 Xtal 50M 70 Xtal 100M 130 RC 10M 10 RC 32M 32 Typical Consumption (mA) Max 1 MG2 3V 0.4 0 1.5 3 ...

Page 4

... A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers. MG2 4 4137O–AERO–06/05 ...

Page 5

... Atmel offers a wide range of packaging options which are listed below: Table 3. Packaging Options Notes: 4137O–AERO–06/05 (1) Package Type CQPF MQFP 1. Contact Atmel Local Design Centers to check the availability of the matrix/package combination. 2. Contact factory. Pins Lead Spacing Min./Max (mils) 132 25,6 160 25,6 196 25 256 20 352 20 MG2 5 ...

Page 6

... Design Flows and Tools Design Flows and A generic design flow for an MG2 array is illustrated below. Modes A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step, structural verification is performed which includes the following tasks: • ...

Page 7

... Figure 1. MG2 Design Flow 4137O–AERO–06/05 System Specifications RTL Simulation Logic Synthesis Floor Plan Bonding Diagram Gate Level Simulation Scan Insertion ATG and Fault Simulation Placement JTAG Insertion Clock Tree Synthesis Routing & Extract Back Annotated Simulation Sign-off Samples Manufacturing ...

Page 8

... Mentor/Modelsim (RTL and gate), Velocity, BSD Archictect, Flex Test • Synopsys/Design Compiler, Prime Time • Vital Table 4. Design Kit Description MG2 8 Design Tool or Library Design manual and libraries Synthesis library Gate level simulation library Design rules analyzer Power consumption analyzer ...

Page 9

... Junction temperature ....................................... TJ < 20°C Storage temperature ...................................... -65°C to +150°C TLL/CMOS: Supply voltage VDD..............................................-0.5V to +7V I/O voltage ............................................... -0.5V to VDD + 0.5V 4137O–AERO–06/05 *NOTE: Stresses above those listed may cause perma- nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MG2 9 ...

Page 10

... Leakage current per cell ICCOP Operating current per cell Notes: 1. According buffer: Bout24,Bout12, Bout6, Bout3. 2. Supplied as a design limit but not guarantedd or tested. No more than one outout may be shorted at a time for a maximum duration of 10 seconds. 3. Without Schmitt trigger. MG2 10 Min. Typ 0 – 0 3.5 – ...

Page 11

... IOH = -10,-4, - – 2.2 V 1.2 – – V 0.8 – µA µ µA 150 – +1 µA 50 100 – 155 mA 310 0 0.2 0.25 µA/MHz MG2 Conditions – – (1) (1) – – – – – – BOUT3 BOUT6 BOUT12 BOUT24 – – 11 ...

Page 12

... AC Characteristics Table 7. AC Characteristics TJ = 25°C Table 8. AC Characteristics TJ = 25°C MG2 12 Process Typical (all values Buffer Description BOUT12 Output buffer with 12 mA drive Process Typical (all values Cell Description BINCMOS CMOS input buffer BINTTL TTL input buffer INV ...

Page 13

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...

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