LTC1409 LINER [Linear Technology], LTC1409 Datasheet - Page 14

• Manufacturer Part Number: LTC1409
• Description: 12-Bit, 800ksps Sampling A/D Converter with Shutdown
• Manufacturer: LINER [Linear Technology]

LTC1409
A
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1409, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the OV
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
14
PPLICATI
DD
bypass capacitor should also be connected to
CIRCUITRY
O
ANALOG
INPUT
U
S
I FOR ATIO
1
+
–
U
+A
+
IN
2
–A
IN
10 F
REFCOMP
W
4
Figure 12. Power Supply Grounding Practice
0.1 F
AGND
5
ANALOG GROUND PLANE
+
U
10 F
LTC1409
V
SS
26
0.1 F
The LTC1409 has differential inputs to minimize noise
coupling. Common mode noise on the +A
will be rejected by the input CMRR. The –A
used as a ground sense for the +A
will hold and convert the difference voltage between +A
and –A
be kept as short as possible. In applications where this is
not possible, the +A
by-side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10 F bypass
capacitors should be used at the V
as shown in the Typical Application on the first page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively 10 F tantalum
capacitors in parallel with 0.1 F ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figure 13a, 13b, 13c and 13d show the schematic and
layout of a suggested evaluation board. The layout demon-
strates the proper use of decoupling capacitors and ground
plane with a two layer printed circuit board.
+
10 F
IN
. The leads to +A
AV
DD
28
0.1 F
OV
DD
27
IN
DGND
and –A
14
OGND
IN
19
(Pin 1) and –A
IN
traces should be run side-
DD
IN
DIGITAL
SYSTEM
and REFCOMP pins
input; the LTC1409
LTC1409 • F12
IN
IN
IN
and –A
(Pin 2) should
input can be
IN
leads
IN