LTC1530 LINER [Linear Technology], LTC1530 Datasheet - Page 16

• Manufacturer Part Number: LTC1530
• Description: High Power Synchronous Switching Regulator Controller
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC1530
Thermal Considerations
Limit the LTC1530’s junction temperature to less than
125 C. The LTC1530’s SO-8 package is rated at 130 C/W
and care must be taken to ensure that the worst-case input
voltage and gate drive load current requirements do not
cause excessive die temperatures. Short-circuit or fault
conditions may activate the internal thermal shutdown
circuit.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board (PCB), the
following checklist should be used to ensure proper
operation of the LTC1530. These items are illustrated
graphically in the layout diagram of Figure 9. The thicker
lines show the high current power paths. Note that at 10A
current levels or above, current density in the PCB itself is
a serious concern. Traces carrying high current should be
as wide as possible. For example, a PCB fabricated with
2oz copper requires a minimum trace width of 0.15" to
carry 10A, and only if trace length is kept short.
1. In general, begin the layout with the location of the
2. Tie the GND pin to the ground plane at a single point,
16
power devices. Orient the power circuitry so that a clean
power flow path is achieved. Maximize conductor widths
but minimize conductor lengths. Keep high current
connections on one side of the PCB if possible. If not,
minimize the use of vias and keep the current density in
the vias to <1A/via, preferably < 0.5A/via. After achiev-
ing a satisfactory power path layout, proceed with the
control circuitry layout. It is much easier to find routes
for the relatively small traces in the control circuits than
it is to find circuitous routes for high current paths.
preferably at a fairly quiet point in the circuit, such as the
bottom of the output capacitors. However, this is not
U
U
W
U
3. Locate the small signal resistor and capacitors used for
4. Place the PV
5. Connect the (+) plate of C
6. The V
7. Kelvin sense I
8. Minimize the length of the gate lead connections.
always practical due to physical constraints. Connect
the low side source to the input capacitor ground.
Connect the input and output capacitor to the ground
plane. Run a separate trace for the low side FET source
to the input capacitors. Do not tie this single point
ground in the trace run between the low side FET source
and the input capacitor ground. This area of the ground
plane is very noisy.
frequency compensation close to the COMP pin. Use a
separate ground trace for these components that ties
directly to the GND pin of the LTC1530. Do not connect
these components to the ground plane!
LTC1530 as possible. The 10 F bypass capacitor shown
at PV
by minimizing ripple at the PV
drain of the upper MOSFET. LTC recommends an
additional 1 F low ESR ceramic capacitor between V
and power ground.
switching node. Care must be taken to isolate this pin
from capacitive coupling to the high current inductor
switching signals. A 0.1 F is recommended between
the V
fixed voltage versions. For the adjustable voltage ver-
sion, keep the resistor divider close to the LTC1530.
The bottom resistor’s ground connection should tie
directly to the LTC1530’s GND pin.
of Q1.
OUT
CC
SENSE
helps provide optimum regulation performance
pin and the GND pin directly at the LTC1530 for
/V
CC
OUT
MAX
decoupling capacitor as close to the
pin is very sensitive to pickup from the
and I
FB
IN
at the drain and source pins
as close as possible to the
CC
pin.
IN