LTC1746 LINER [Linear Technology], LTC1746 Datasheet - Page 16

• Manufacturer Part Number: LTC1746
• Description: Low Power,14-Bit, 25Msps ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC1746
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
3. If the ADC is clocked with a sinusoidal signal, filter the
4. Balance the capacitance and series resistance at both
The encode inputs have a common mode range of 1.8V to
V
single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1746 is 25Msps. For
the ADC to operate properly the encode signal should have
a 50% ( 5%) duty cycle. Each half cycle must have at least
19ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
16
DD
coupled use a higher turns ratio to increase the
amplitude.
encode signal to reduce wideband noise.
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
. Each input may be driven from ground to V
U
U
LATCH
FROM
DATA
OE
W
Figure 9. Equivalent Circuit for a Digital Output Buffer
PREDRIVER
LOGIC
V
DD
U
DD
for
V
DD
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
At sample rates slower than 25Msps the duty cycle can
vary from 50% as long as each half cycle is at least 19ns.
The lower limit of the LTC1746 sample rate is determined
by the droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals
on small valued capacitors. Junction leakage will dis-
charge the capacitors. The specified minimum operating
frequency for the LTC1746 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50 to external
circuitry and may eliminate the need for external damping
resistors.
OV
DD
LTC1746
43
1746 F09
OV
OGND
DD
0.1 F
0.5V TO
V
TYPICAL
DATA
OUTPUT
DD
DD
and OGND, iso-
1746f