LTC1879 LINER [Linear Technology], LTC1879 Datasheet - Page 15

• Manufacturer Part Number: LTC1879
• Description: 1.2A Synchronous Step-Down Regulator with 15mA Quiescent Current
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
PC Board Layout Checklist
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. Figure 8 is a
sample of PC board layout for the design example shown
in Figure 9. A 4-layer PC board is used in this design.
Several guidelines are followed in this layout:
1. In order to minimize switching noise and improve
2. Beware of ground loops in multiple layer PC boards. Try
output load regulation, the PGND pins of the LTC1879
should be connected directly to 1) the negative terminal
of the output decoupling capacitors, 2) the negative
terminal of the input capacitor and 3) vias to the ground
plane immediately adjacent to Pins 1, 7 and 10. The
ground trace on the top layer of the PC board should be
as wide and short as possible to minimize series resis-
tance and inductance.
to maintain one central ground node on the board and
use the input capacitor to avoid excess input ripple for
high output current power supplies. If the ground is to
be used for high DC currents, choose a path away from
the small-signal components.
U
U
R
R
R
FB2
FB1
C
SS
Figure 8. Typical Application and Suggested Layout (Topside Only)
IN1
C
VIAS TO GND PLANE
SS
V
W
IN
U
C
C1
R
C
C
IN2
DUT
C
C2
VIAS TO GND PLANE
C
PL
3. The high di/dt loop from the top terminal of the input
4. Place the small-signal components away from high
5. For optimum load regulation and true sensing, the top
R
capacitor, through the power MOSFETs and back to the
input capacitor should be kept as tight as possible to
reduce inductive ringing. Excess inductance can cause
increased stress on the power MOSFET and increase
noise on the input. If low ESR ceramic capacitors are
used to reduce input noise, place these capacitors close
to the DUT in order to keep the series inductance to a
minimum.
frequency switching nodes. In the layout shown in
Figure 8, all of the small-signal components have been
placed on one side of the IC and all of the power
components have been placed on the other.
of the output resistor divider should connect indepen-
dently to the top of the output capacitor (Kelvin connec-
tion), staying away from any high dV/dt traces. Place
the divider resistors near the LTC1879 in order to keep
the high impedance FB node short.
PL
PGND
R
SVIN
R
C
PG
OUT
VIA CONNECTION TO R
L1
V
OUT
FB1
1879 F08
LTC1879
15
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