LT1713 LINER [Linear Technology], LT1713 Datasheet - Page 4

• Manufacturer Part Number: LT1713
• Manufacturer: LINER [Linear Technology]

LT1713/LT1714
ELECTRICAL CHARACTERISTICS
The
V
SYMBOL PARAMETER
V
CMRR
PSRR
PSRR
A
V
V
I
I
V
V
I
t
t
t
t
t
t
t
f
t
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1713C/LT1714C are guaranteed to meet specified
performance from 0 C to 70 C. They are designed, characterized and
expected to meet specified performance from – 40 C to 85 C but are not
tested or QA sampled at these temperatures. The LT1713I/LT1714I are
guaranteed to meet specified performance from – 40 C to 85 C.
Note 3: The negative supply should not be greater than the ground pin
voltages and the maximum voltage across the positive and negative
supplies should not be greater than 12V.
Note 4: Input offset voltage (V
voltages measured by forcing first one output, then the other to V
Note 5: Input bias current (I
currents.
4
IL
PD
r
f
LPD
SU
H
DPW
MAX
JITTER
+
–
CM
V
OH
OL
IH
IL
t
+
PD
= 5V, V
+
–
denotes specifications which apply over the full operating temperature range, otherwise specifications are at T
Input Voltage Range
Common Mode Rejection Ratio
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Small-Signal Voltage Gain (Note 10)
Output Voltage Swing HIGH (Note 8)
Output Voltage Swing LOW (Note 8)
Positive Supply Current (Per Comparator)
Negative Supply Current (Per Comparator)
Latch Pin High Input Voltage
Latch Pin Low Input Voltage
Latch Pin Current
Propagation Delay (Note 6)
Differential Propagation Delay (Note 6)
Output Rise Time
Output Fall Time
Latch Propagation Delay (Note 7)
Latch Setup Time (Note 7)
Latch Hold Time (Note 7)
Minimum Latch Disable Pulse Width (Note 7)
Maximum Toggle Frequency
Output Timing Jitter
–
= – 5V, V
CM
= 0V, V
B
) is defined as the average of the two input
OS
) is defined as the average of the two
LATCH
= 0.8V, C
LOAD
= 10pF, V
CONDITIONS
– 5V V
2.4V V
– 7V V
1V V
I
I
I
I
V
V
V
10% to 90%
90% to 10%
V
V
OUT
OUT
OUT
OUT
OVERDRIVE
OVERDRIVE
LATCH
IN
IN
V
V
V
V
IN
IN
IN
IN
= 100mV
= 630mV
= 1mA, V
= 10mA, V
= – 1mA, V
= – 10mA, V
= 100mV, V
= 100mV, V
= 100mV, V
= 100mV, V
+
OUT
/2.
= V
CM
–
+
OVERDRIVE
+
= 1V
= 1V
0V, V
7V, V
4V, R
P-P
P-P
5V
OVERDRIVE
OVERDRIVE
OVERDRIVE
Sine Wave
(0dBm) Sine Wave, f = 30MHz
OVERDRIVE
OVERDRIVE
OVERDRIVE
OVERDRIVE
OVERDRIVE
CM
CM
L
=
Note 6: Propagation delay (t
the actual V
requirements, the LT1713/LT1714 propagation delay is specified with a
1k load to ground for 5V supplies, or to mid-supply for 2.7V or 5V
single supplies.
Note 7: Latch propagation delay (t
respond when the latch pin is deasserted. Latch setup time (t
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (t
which the input signal must remain stable. Latch disable pulse width
(t
latches in new data on the data inputs.
= 5V
= – 5V
t
DPW
= 20mV, unless otherwise specified.
PD
= 50mV
= 50mV
= t
= 50mV
) is the width of the negative pulse on the latch enable pin that
= 50mV
= 20mV
= 20mV
= 5mV
= 20mV
PD
+
OS
– t
. Differential propagation delay is defined as:
PD
–
. Load capacitance is 10pF. Due to test system
PD
H
) is measured with the overdrive added to
) is the interval after the latch is asserted in
LPD
– 5.1
MIN
1.5
4.5
4.3
2.4
) is the delay time for the output to
62
60
68
65
65
60
0.20
0.35
TYP
4.8
4.6
5.5
3.5
8.5
0.5
1.5
70
80
80
65
15
3
7
4
4
8
0
8
A
= 25 C.
MAX
5.1
0.4
0.5
7.5
9.0
4.5
5.0
0.8
10
10
12
3
SU
) is the
UNITS
ps
V/mV
MHz
RMS
mA
mA
mA
mA
dB
dB
dB
dB
dB
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V
V
V
A