LTC2207 LINER [Linear Technology], LTC2207 Datasheet - Page 24

• Manufacturer Part Number: LTC2207
• Description: 16-Bit, 105Msps/80Msps ADCs
• Manufacturer: LINER [Linear Technology]

LTC2207/LTC2206
APPLICATIONS INFORMATION
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise fl oor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output Randomizer function is active
when the RAND pin is high.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OV
24
ANALOG
INPUT
AIN
AIN
+
–
DD
LTC2207/LTC2206
Figure 13. Functional Equivalent Block Diagram of Internal Dither Circuit
should be tied to that same
CLOCK/DUTY
ENC
CONTROL
AMP
S/H
CYCLE
+
ENC
–
DD
, should be tied
PRECISION
PIPELINED
ADC CORE
16-BIT
DAC
1.8V supply. In CMOS mode OV
any logic voltage up to the V
powered with any voltage from ground up to 1V and must
be less than OV
OGND and OV
Internal Dither
The LTC2207/LTC2206 are 16-bit ADCs with a very lin-
ear transfer function; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the input
location on the ADC transfer curve, resulting in improved
SFDR for low signal levels.
As shown in Figure 15, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
the noise fl oor of the ADC, as compared to the noise fl oor
with dither off.
SUMMATION
DIGITAL
DD
DD
.
PSEUDO-RANDOM
HIGH = DITHER ON
LOW = DITHER OFF
. The logic outputs will swing between
MULTIBIT DEEP
DITHER ENABLE
GENERATOR
NUMBER
DRIVERS
OUTPUT
DITH
DD
22076 F13
of the ADC. OGND can be
DD
CLKOUT
can be powered with
D15
D0
OF
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