LTC2225 LINER [Linear Technology], LTC2225 Datasheet - Page 14

• Manufacturer Part Number: LTC2225
• Description: 12-Bit, 10Msps Low Power 3V ADC
• Manufacturer: LINER [Linear Technology]

LTC2225
APPLICATIO S I FOR ATIO
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2225 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OV
from the digital outputs.
Data Format
Using the MODE pin, the LTC2225 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3V
binary output format. Connecting MODE to
2/3V
An external resistor divider can be used to set the 1/3V
or 2/3V
the MODE pin.
14
LATCH
LTC2225
FROM
DATA
OE
DD
DD
or V
PREDRIVER
DD
LOGIC
logic values. Table 2 shows the logic states for
V
DD
DD
voltages will also help reduce interference
Figure 9. Digital Output Buffer
selects 2’s complement output format.
U
U
V
DD
W
OV
DD
DD
and OGND, iso-
DD
43Ω
selects offset
2225 F09
U
OV
OGND
DD
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
0.1µF
DD
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OV
OV
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OV
swing between OGND and OV
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The output
Hi-Z state can be used to multiplex the data bus of several
LTC2225s.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
Table 2. MODE Pin Function
MODE Pin
0
1/3V
2/3V
V
DD
DD
DD
DD
can be powered with any voltage from 500mV up to
DD
2’s Complement
2’s Complement
Output Format
Offset Binary
Offset Binary
should be tied to that same 1.8V supply.
DD
DD
.
. The logic outputs will
Cycle Stablizer
DD
Clock Duty
DD
, should be tied
Off
On
On
Off
and OE to V
DD
and OE
2225fa
DD