LT1801 LINER [Linear Technology], LT1801 Datasheet - Page 14

• Manufacturer Part Number: LT1801
• Description: Dual/Quad 80MHz, 25V/?s Low Power Rail-to-Rail Input and Output Precision Op Amps
• Manufacturer: LINER [Linear Technology]

LT1801/LT1802
14
APPLICATIO S I FOR ATIO
Circuit Description
The LT1801/LT1802 have an input and output signal range
that covers from the negative power supply to the positive
power supply. Figure 1 depicts a simplified schematic of
the amplifier. The input stage is comprised of two differ-
ential amplifiers, a PNP stage Q1/Q2 and an NPN stage Q3/
Q4 that are active over the different ranges of common
mode input voltage. The PNP differential pair is active
between the negative supply to approximately 1.2V below
the positive supply. As the input voltage moves closer
toward the positive supply, the transistor Q5 will steer the
tail current I
NPN differential pair and the PNP pair becomes inactive
for the rest of the input common mode range up to the
positive supply. Also at the input stage, devices Q17 to
Q19 act to cancel the bias current of the PNP input pair.
When Q1-Q2 are active, the current in Q16 is controlled to
be the same as the current in Q1-Q2, thus the base current
of Q16 is nominally equal to the base current of the input
devices. The base current of Q16 is then mirrored by
devices Q17-Q19 to cancel the base current of the input
devices Q1-Q2.
V
V
+
–
Q16
+
I
2
1
to the current mirror Q6/Q7, activating the
+IN
–IN
Q17
U
Q18
ESDD1
ESDD4
U
V
V
+
–
V
V
–
+
ESDD2
ESDD3
Figure 1. LT1801/LT1802 Simplified Schematic Diagram
W
D6
D5
D8
D7
Q19
U
Q4
Q7
D1
D2
Q3
Q5
Q6
A pair of complementary common emitter stages Q14/
Q15 that enable the output to swing from rail to rail
constructs the output stage. The capacitors C2 and C3
form the local feedback loops that lower the output imped-
ance at high frequency. These devices are fabricated on
Linear Technology’s proprietary high speed complemen-
tary bipolar process.
Power Dissipation
The LT1801 amplifier is offered in a small package, SO-8,
which has a thermal resistance of 190°C/W, θ
is a need to ensure that the die’s junction temperature
should not exceed 150°C. Junction temperature T
calculated from the ambient temperature T
pation P
The power dissipation in the IC is the function of the supply
voltage, output voltage and the load resistance. For a given
supply voltage, the worst-case power dissipation P
occurs at the maximum supply current and the output
V
BIAS
T
J
Q1
+
= T
D3
D4
Q2
D
I
A
1
and thermal resistance θ
+ (P
Q10
D
• θ
Q11
JA
)
Q9
R3
R1
Q12
Q8
R4
R2
C
C
+
V
OUTPUT BIAS
Q13
–
R5
JA
BUFFER
I
3
AND
:
C2
C1
A
, power dissi-
18012 F01
JA
Q15
. So there
Q14
OUT
DMAX
18012fb
J
is