LTC2259CUJ-12-PBF LINER [Linear Technology], LTC2259CUJ-12-PBF Datasheet - Page 16

• Manufacturer Part Number: LTC2259CUJ-12-PBF
• Description: 12-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
• Manufacturer: LINER [Linear Technology]

LTC2261-12
LTC2260-12/LTC2259-12
PIN FUNCTIONS
CLKOUT
CLKOUT
normally transition at the same time as the falling and ris-
ing edges of CLKOUT
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not
connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
16
FUNCTIONAL BLOCK DIAGRAM
SENSE
0.1μF
1μF
V
A
A
V
REF
IN
IN
CM
+
–
–
+
(Pin 28): Data Output Clock. The digital outputs
(Pin 27): Inverted version of CLKOUT
INPUT
REFERENCE
S/H
SELECT
RANGE
1.25V
V
DD
/2
REF
BUF
+
. The phase of CLKOUT
FIRST PIPELINED
ADC STAGE
DIFF
AMP
REF
SECOND PIPELINED
ADC STAGE
0.1μF
REFH
Figure 1. Functional Block Diagram
REFH
+
0.1μF
2.2μF
+
can also
.
REFL
THIRD PIPELINED
REFL
ADC STAGE
0.1μF
INTERNAL CLOCK SIGNALS
CLOCK/DUTY
ENC
CONTROL
CYCLE
+
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1
23/24, 29/30, 31/32, 33/34): Double Data Rate Digital
Outputs. Two data bits are multiplexed onto each differential
output pair. The even data bits (D0, D2, D4, D6, D8, D10)
appear when CLKOUT
D5, D7, D9, D11) appear when CLKOUT
CLKOUT
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT
CLKOUT
by programming the mode control registers.
OF
is high when an overfl ow or underfl ow has occurred.
ENC
–
/OF
–
FOURTH PIPELINED
–
/D0_1
ADC STAGE
+
+
–
PAR/SER
(Pins 35/36): Over/Under Flow Digital Output. OF
/CLKOUT
can also be delayed relative to the digital outputs
+
to D10_11
CS
REGISTERS
CONTROL
MODE
SCK
+
FIFTH PIPELINED
SDI
ADC STAGE
(Pins 27/28): Data Output Clock.
+
SDO
is low. The odd data bits (D1, D3,
–
/D10_11
AND CORRECTION
SHIFT REGISTER
DRIVERS
OUTPUT
+
(Pins 19/20, 21/22,
OGND
+
is high.
+
226112 F01
. The phase of
•
•
•
OV
GND
OF
D11
D0
CLKOUT
CLKOUT
V
DD
DD
226112f
+
–
+