LT1947 LINER [Linear Technology], LT1947 Datasheet - Page 4
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LT1947
Manufacturer Part Number
LT1947
Description
Adjustable Output TFT-LCD Triple Switching Regulator
Manufacturer
LINER [Linear Technology]
Datasheet
1.LT1947.pdf
(8 pages)
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BLOCK DIAGRA
PI FU CTIO S
FB1 (Pin 1): Feedback Pin for First Switcher. Connect
resistor divider tap here. Set AV
AV
FB2 (Pin 2): Feedback Pin for Second Switcher. Connect
resistor divider 2 here and set V
V
C
from C
reaching 1.26V to V
SW1 (Pin 4): AV
(see Figure 1). Minimize trace area at this pin to keep EMI
down.
GND (Pin 5): Ground. Connect directly to local ground
plane.
LT1947
4
ON
T
DD
(Pin 3): Timing Capacitor Pin. Connect a 10nF capacitor
U
= 1.26V (1 + R3/R4) – 160mV.
OSCILLATOR
= 1.26V(1 + R1/R2).
V
V
T
ON
O2
3MHz
to ground to program a 2.3ms delay from FB1
U
Q3
DD
OSC
SLOPE 1
SLOPE 2
Switch Node. Connect L1 and D1 here
ON
U
turning on.
C
W
T
–
+
1.26V REFERENCE
UNDERVOLTAGE
REF
LOCKOUT
Q4
AND
DD
5.5 A
according to:
ON
REF
–
+
using:
FB1
FB2
28mV
+ –
REF
REF
REF
V
ceramic capacitor close to the pin.
SW2 (Pin 7): V
Minimize trace area at this pin to keep EMI down.
SHDN (Pin 8): Pull this pin low for shutdown mode. For
normal operation, tie to a voltage between 2.4V and 8V.
V
connected to the emitter of Q3 (see Block Diagram), the
high side switch between V
V
reaches its programmed voltage after the internal timer
times out.
–
+
–
+
IN
O2
ON
(Pin 6): Input Supply Pin. Must be bypassed with a
(Pin 9): SW2 Output. This node is also internally
(Pin 10): This is the delayed output for SW2. V
O2
V
V
IN
IN
Switch Node. Connect L2 and D2 here.
–
+
–
+
SLOPE 1
SLOPE 2
+
+
+
+
O2
and V
GND
R
R
OSC
OSC
S
S
ON
Q
Q
.
SHUTDOWN
SHDN
SW1
SW2
Q1
Q2
0.01
0.03
1947BD
1947f
ON