LTC2446 LINER [Linear Technology], LTC2446 Datasheet - Page 6

• Manufacturer Part Number: LTC2446
• Description: 24-Bit High Speed 8-Channel ?? ADCs with Selectable Multiple Reference Inputs
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
LTC2446/LTC2447
– 0.3V to V
inputs (IN
IN
range, the converter produces unique over-range and
under-range output codes.
CH0 to CH7 (Pins 8, 9, 12, 13, 16, 17, 20, 21): Analog
Inputs. May be programmed for Single-ended or Differen-
tial mode.
V
V
V
Inputs. The voltage on these pins can be anywhere
between 0V and V
input (V
the corresponding negative reference input (V
V
NC (Pins 24, 25, 26, 27): LTC2446 No Connect. These
pins can either be tied to ground or left floating.
MUXOUTP (Pin 24): LTC2447 Positive Input Channel
Multiplexer Output. Used to drive the input to an external
buffer/amplifier for the selected positive input signal (IN
ADCINP (Pin 25): LTC2447 Positive ADC Input. Tie to
output of buffer/amplifier driven by MUXOUTP.
ADCINN (Pin 26): LTC2447 Negative ADC Input. Tie to
output of buffer/amplifier driven by MUXOUTN.
MUXOUTN (Pin 27): LTC2447 Negative Input Channel
Multiplexer Output. Used to drive the input to an external
buffer/amplifier for the selected negative input signal
(IN
V
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
V
This differential reference input can be used for any input
channel selected through a single bit in the digital input word.
SDI (Pin 34): Serial Data Input. This pin is used to select
the speed, 1x or 2x mode, resolution, input channel and
reference input for the next conversion cycle. At initial
power-up, the default mode of operation is CH0-CH1,
V
6
REFG
REF01
REF23
REF67
REF23
CC
REF01
+
U
–
– IN
).
(Pin 28): Positive Supply Voltage. Bypass to GND with
+
, OSR of 256, and 1x mode. The serial data input
–
+
–
+
(Pin 29), V
–
, V
(Pin 23), V
EF01
) from –0.5 • V
(Pin 14), V
(Pin 11), V
+
U
CC
REF45
and IN
+
, V
+ 0.3V. Within these limits, the two selected
REF23
–
, V
–
REFG
REF67
CC
) provide a bipolar input range (V
REF67
REF45
U
REF01
+
as long as the positive reference
, V
REF
–
–
(Pin 30): Global Reference Input.
REF45
–
(Pin 22): Differential Reference
+
to 0.5 • V
–
) by at least 100mV.
(Pin 19), V
(Pin 10) V
+
, V
REF67
REF
. Outside this input
+
REF23
REF45
) is greater than
+
–
(Pin 15),
(Pin 18),
REF01
IN
+
–
).
=
,
contains an enable bit which determines if a new channel/
speed is selected. If this bit is low the following conversion
remains at the same speed and selected channel. The
serial data input is applied to the device under control of
the serial clock (SCK) during the data output cycle. The
first conversion following a new channel/speed is valid.
F
controls the internal conversion clock. When F
nected to V
oscillator running at 9MHz. The conversion rate is deter-
mined by the selected OSR such that t
OSR + 170)/f
at 8/t
60Hz) at OSR = 32768. This pin may be driven with a
maximum external clock of 10.24MHz resulting in a maxi-
mum 8kHz output rate (OSR = 64, 2x Mode).
CS (Pin 36): Active Low Chip Select. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as long
as CS is HIGH. A LOW-to-HIGH transition on CS during the
Data Output aborts the data transfer and starts a new
conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
high impedance state. During the conversion and sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS
LOW. This signal is HIGH while the conversion is in
progress and goes LOW once the conversion is complete.
SCK (Pin 38): Bidirectional Digital Clock Pin. In internal
serial clock operation mode, SCK is used as a digital output
for the internal serial interface clock during the data output
period. In the external serial clock operation mode, SCK is
used as the digital input for the external serial interface
clock during the data output period. The serial clock
operation mode is determined by the logic level applied to
the EXT pin.
Exposed Pad (Pin 39): Ground. The exposed pad on the
bottom of the package must be soldered to the PCB ground.
For Prototyping purposes, this pin may remain floating.
O
(Pin 35): Frequency Control Pin. Digital input that
CONV
, 7kHz at OSR = 256 and 55Hz (Simultaneous 50/
CC
OSC
or GND, the converter uses its internal
(kHz). The first digital filter null is located
CC
) the SDO pin is in a
CONV
(ms) = (40 •
O
is con-
24467fa