LTC2604 LINER [Linear Technology], LTC2604 Datasheet - Page 11

• Manufacturer Part Number: LTC2604
• Description: Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP
• Manufacturer: LINER [Linear Technology]

INPUT WORD (LTC2604)
INPUT WORD (LTC2614)
INPUT WORD (LTC2624)
OPERATIO
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy chain” series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire chain.
Because of this, the devices can be addressed and con-
trolled individually by simply concatenating their input
words; the first instruction addresses the last device in the
chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the first
device as the data input. When the data transfer is com-
plete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.
C3
C3
C3
COMMAND
COMMAND
COMMAND
C2
C2
C2
C1 C0
C1 C0
C1 C0
U
A3
A3
A3
ADDRESS
ADDRESS
ADDRESS
A2
A2
A2
A1
A1
A1
A0
A0
A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
MSB
MSB
MSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D15
D14
D13
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
DATA (12 BITS + 4 DON’T-CARE BITS)
DATA (14 BITS + 2 DON’T-CARE BITS)
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four outputs are needed. When in power-down, the
buffer amplifiers, bias circuits and reference inputs are
disabled, and draw essentially zero current. The DAC
outputs are put into a high-impedance state, and the
output pins are passively pulled to ground through indi-
vidual 90k resistors. Input- and DAC-register contents are
not disturbed during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100
tion with the appropriate DAC address, (n). The 16-bit data
word is ignored. The supply current is reduced by approxi-
mately 1/4 for each DAC powered down. The effective
resistance at REF x (pins 3, 6, 12 and 15) are at high-
impedance input (typically > 1G ) when the correspond-
ing DACs are powered down.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state is
powered up and updated, normal settling is delayed. If less
than four DACs are in a powered-down state prior to the
update command, the power-up delay time is 5 s. If on the
LTC2604/LTC2614/LTC2624
DATA (16 BITS)
D1 D0
LSB
D1 D0
X
LSB
X
D1 D0
X
X
b
2604 TBL03
2604 TBL01
2604 TBL02
in combina-
LSB
X
X
11
2604f