S3S12HZ256J3CAA FREESCALE [Freescale Semiconductor, Inc], S3S12HZ256J3CAA Datasheet - Page 158
S3S12HZ256J3CAA
Manufacturer Part Number
S3S12HZ256J3CAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.S3S12HZ256J3CAA.pdf
(692 pages)
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Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.8.4
Read: anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PV[7:0].
4.3.8.5
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
158
SRRV[7:0]
PERV[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
SRRV7
PERV7
Slew Rate Port V
0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
Pull Device Enable Port V
0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Port V Slew Rate Register (SRRV)
Port V Pull Device Enable Register (PERV)
0
0
7
7
SRRV6
PERV6
Figure 4-53. Port V Pull Device Enable Register (PERV)
0
0
6
6
Figure 4-52. Port V Slew Rate Register (SRRV)
Table 4-37. SRRV Field Descriptions
Table 4-38. PERV Field Descriptions
SRRV5
PERV5
MC9S12HZ256 Data Sheet, Rev. 2.04
0
0
5
5
SRRV4
PERV4
0
0
4
4
Description
Description
SRRV3
PERV3
0
0
3
3
SRRV2
PERV2
0
0
2
2
SRRV1
PERV1
Freescale Semiconductor
0
0
1
1
SRRV0
PERV0
0
0
0
0
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