S3S12HZ256J3CAA FREESCALE [Freescale Semiconductor, Inc], S3S12HZ256J3CAA Datasheet - Page 569
S3S12HZ256J3CAA
Manufacturer Part Number
S3S12HZ256J3CAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.S3S12HZ256J3CAA.pdf
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20.2
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and
XIRQ pin data.
20.3
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
20.3.1
20.3.2
20.3.2.1
Read: See individual bit descriptions
Write: See individual bit descriptions
Freescale Semiconductor
Reset
W
R
External Signal Description
Memory Map and Register Definition
Address
0x0015
0x0016
0x001F
Offset
Module Memory Map
Register Descriptions
Interrupt Test Control Register
0
0
7
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
= Unimplemented or Reserved
0
0
6
Figure 20-2. Interrupt Test Control Register (ITCR)
MC9S12HZ256 Data Sheet, Rev. 2.04
0
0
5
Table 20-1. INT Memory Map
WRTINT
0
4
Use
ADR3
1
3
ADR2
1
2
Chapter 20 Interrupt (INTV1)
ADR1
1
1
Access
R/W
R/W
R/W
ADR0
1
0
569
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