LTC3413 LINER [Linear Technology], LTC3413 Datasheet - Page 12

• Manufacturer Part Number: LTC3413
• Description: 3A, 2MHz Monolithic Synchronous Regulator for DDR/QDR Memory Termination
• Manufacturer: LINER [Linear Technology]

LTC3413
APPLICATIO S I FOR ATIO
adequate for most applications. Connect the V
directly to SV
will set the output voltage equal to one-half of the voltage
on the V
example is illustrated in Figure 3.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3413. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning to
12
REF
IN
pin. The complete circuit for this design
. Connecting the V
U
U
Figure 3. One-Half V
(Efficiency Curve is Shown in Figure 1b)
PGOOD
FB
W
**TDK C4532X5R0J107M
*VISHAY DALE IHLP-2525CZ-01 0.47 H
2200pF
pin directly to V
330pF X7R
C
X7R
R
4.7M
309k
R
ITH
OSC
SS
5.11k
R
100pF
C
ITH
SS
C
R
100k
C
PG
REF
U
, 3A DDR Memory Termination Supply at 1MHz
1
2
3
4
5
6
7
8
REF
SV
PGOOD
I
V
R
V
RUN/SS
SGND
TH
FB
REF
T
IN
OUT
pin
LTC3413
SWV
PGND
PGND
PV
PV
SW
SW
SW
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3413.
2. Connect the (+) terminal of the input capacitor(s), C
as close as possible to the PV
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PV
your system).
5. Connect the V
FB
IN
IN
16
15
14
13
12
11
10
9
100 F
C
IN
IN2
, SV
**
C
100 F
IN1
3413 F03
IN
0.47 H
**
, V
L1*
FB
OUT
pin directly to the V
GND
, PGND, SGND or any other DC rail in
C
100 F
OUT
2
**
V
1.25V
V
2.5V
OUT
3A
IN
IN
pin. This capacitor
OUT
pin.
sn3413 3413fs
IN
,