LTC3633 LINER [Linear Technology], LTC3633 Datasheet - Page 19

• Manufacturer Part Number: LTC3633
• Description: Dual Channel 3A, 15V Monolithic Synchronous Step-Down Regulator
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3633 circuits: 1) I
losses and quiescent power loss 3) transition losses and
other losses.
1. I
2. The internal LDO supplies the power to the INTV
% Effi ciency = 100% – (L1 + L2 + L3 +…)
the internal switches, R
In continuous mode, the average output current fl ows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET R
cycle (DC) as follows:
The R
obtained from the Typical Performance Characteristics
curves. Thus to obtain I
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from
V
INTV
bias current. In continuous mode, I
where Q
top and bottom power MOSFETs and f is the switching
frequency. For estimation purposes, (Q
LTC3633 regulator channel is approximately 2.3nC.
2
IN
R losses are calculated from the DC resistances of
R
I
2
to ground. The resulting dQ/dt is a current out of
SW
R losses = I
CC
DS(ON)
that is typically much larger than the DC control
= (R
T
and Q
for both the top and bottom MOSFETs can be
DS(ON)TOP
OUT
B
are the gate charges of the internal
2
(R
)(DC) + (R
SW
SW
2
R losses:
, and external inductor, R
+ R
L
2
)
R losses, 2) switching
DS(ON)BOT
GATECHG
DS(ON)
T
+ Q
and the duty
)(1 – DC)
= f(Q
B
) on each
T
CC
+ Q
rail.
B
L
),
.
3. Other “hidden” losses such as transition loss, cop-
Thermal Considerations
The LTC3633 requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to
provide good thermal contact. This gives the QFN and
TSSOP packages exceptional thermal properties, which
are necessary to prevent excessive self-heating of the part
in normal operation.
In a majority of applications, the LTC3633 does not dis-
sipate much heat due to its high effi ciency and low thermal
resistance of its exposed-back QFN package. However, in
applications where the LTC3633 is running at high ambi-
ent temperature, high V
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off until temperature
returns to 140°C.
To prevent the LTC3633 from exceeding the maximum
junction temperature of 125°C, the user will need to do
some thermal analysis. The goal of the thermal analysis
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent cur-
rent and multiply by V
per trace resistances, and internal load currents can
account for additional effi ciency degradations in the
overall power system. Transition loss arises from the
brief amount of time the top power MOSFET spends
in the saturated region during switch node transitions.
The LTC3633 internal power devices switch quickly
enough that these losses are not signifi cant compared
to other sources.
Other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2% total additional loss.
P
LDO
= (I
GATECHG
+ I
IN
IN
, high switching frequency, and
Q
:
) • V
IN
LTC3633
19
3633f