LTC3836 LINER [Linear Technology], LTC3836 Datasheet - Page 22

• Manufacturer Part Number: LTC3836
• Description: Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller
• Manufacturer: LINER [Linear Technology]

LTC3836
APPLICATIONS INFORMATION
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting effi ciency and which change would produce the
most improvement. Effi ciency can be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, fi ve main sources usually account for most of
the losses in LTC3836 circuits: 1) LTC3836 DC bias cur-
rent, 2) MOSFET gate charge current, 3) I
4) transition losses.
1) The V
2) MOSFET gate charge current results from switching the
3) I
4) Transition losses apply to the top MOSFET and increase
Other losses, including C
and inductor core losses, generally account for less than
2% total additional loss.
OPTI-LOOP is a trademark of Linear Technology Corporation.
22
Effi ciency = 100% – (L1 + L2 + L3 + …)
in the electrical characteristics, excluding MOSFET
driver currents. V
increases with V
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE
The resulting dQ/dt is a current out of SENSE
is typically much larger than the DC supply current. In
continuous mode, I
MOSFETs and inductor. In continuous mode, the average
output current fl ows through L but is “chopped” between
the top MOSFET and the bottom MOSFET. The MOSFET
R
the resistance of L to obtain I
with higher operating frequencies and input voltages.
Transition losses can be estimated from:
Transition Loss = 2 (V
2
DS(ON)
R losses are calculated from the DC resistances of the
IN
s multiplied by duty cycle can be summed with
(pin) current is the DC supply current, given
IN
IN
.
GATECHG
current results in a small loss that
IN
IN
and C
)
2
I
O(MAX)
OUT
= f • Q
2
R losses.
ESR dissipative losses
C
RSS
P
.
(f)
2
R losses, and
+
to ground.
+
, which
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (ΔI
resistance of C
charge C
regulator loop then returns V
During this recovery time, V
overshoot or ringing. OPTI-LOOP
the transient response to be optimized over a wide range
of output capacitance and ESR values.
The I
the dominant pole-zero loop compensation. The I
components shown in the Typical Application on the front
page of this data sheet will provide an adequate starting point
for most applications. The values can be modifi ed slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be decided upon
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1μs to
10μs will produce output voltage and I
will give a sense of the overall loop stability. The gain of the
loop will be increased by increasing R
of the loop will be increased by decreasing C
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance. For a detailed explanation of optimiz-
ing the compensation components, including a review of
control loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
Thus a 10μF capacitor would require a 250μs rise time,
limiting the charging current to about 200mA.
TH
OUT
series R
OUT
, causing a rapid drop in V
LOAD
, which generates a feedback error signal. The
OUT
)(ESR), where ESR is the effective series
C
-C
. ΔI
C
OUT
fi lter (see Functional Diagram) sets
LOAD
immediately shifts by an amount
also begins to charge or dis-
OUT
OUT
to its steady-state value.
®
can be monitored for
compensation allows
OUT
TH
C
, and the bandwidth
pin waveforms that
. No regulator can
C
. The output
TH
external
LOAD
3836fa
).