PI7C7300 Pericom Semiconductor Corporation, PI7C7300 Datasheet
PI7C7300
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PI7C7300 Summary of contents
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... PI7C7300A PCI-to-PCI BRIDGE 2380 BERING DRIVE, SAN JOSE, CA 95131 TELEPHONE: 1-877-PERICOM (1-877-737-4266) EMAIL: INTERNET: 3-PORT REVISION 1.09 FAX: 408-435-1100 SOLUTIONS@PERICOM.COM HTTP://WWW.PERICOM.COM ...
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... No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 2 OF 109 09/25/03 Revision 1.09 PI7C7300A ...
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... Ambient temperature corrected in section 0 (maximum ratings) Revised T in section 17.4 and 17.5 SKEW Added web reference to Thermal Characteristics in section 0 Corrected part number references from PI7C7300 to PI7C7300A. Added back PO signal type description on section 3.1 Page 3 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION to 09/25/03 Revision 1 ...
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... MASTER ABORT RECEIVED BY PI7C7300A .................................................................... 35 4.9.3 TARGET TERMINATION RECEIVED BY PI7C7300A ....................................................... 36 4.9.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE........................................................ 36 4.9.3.2 POSTED WRITE TARGET TERMINATION RESPONSE ........................................................... 37 4.9.3.3 DELAYED READ TARGET TERMINATION RESPONSE ......................................................... 38 4.9.4 TARGET TERMINATION INITIATED BY PI7C7300A ....................................................... 38 4.9.4.1 TARGET RETRY............................................................................................................................ 38 4.9.4.2 TARGET DISCONNECT................................................................................................................ 39 4.9.4.3 TARGET ABORT ........................................................................................................................... 40 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 5 OF 109 09/25/03 Revision 1 ...
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... POSTED WRITE TRANSACTIONS...................................................................................... 55 7.3 DATA PARITY ERROR REPORTING SUMMARY ................................................................. 56 7.4 SYSTEM ERROR (SERR#) REPORTING.................................................................................. 60 8 EXCLUSIVE ACCESS...................................................................................................................... 61 8.1 CONCURRENT LOCKS ............................................................................................................. 61 8.2 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300A..................................................... 61 8.2.1 LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION.............................................. 61 8.2.2 LOCKED TRANSACTION IN UPSTREAM DIRECTION.................................................... 63 8.3 ENDING EXCLUSIVE ACCESS ................................................................................................ 63 9 PCI BUS ARBITRATION................................................................................................................. 64 9.1 PRIMARY PCI BUS ARBITRATION......................................................................................... 64 9 ...
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... SAMPLING TIMER REGISTER – OFFSET 7Ch............................................................. 88 14.1.41 SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 80h ......... 88 14.1.42 SECONDARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 84h........ 89 14.1.43 SECONDARY SUCCESSFUL MEMORY READ COUNTER REGISTER – Offset 88h.. 89 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 7 OF 109 09/25/03 Revision 1.09 PI7C7300A ...
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... PRIMARY AND SECONDARY BUSES AT 66MH 17.5 PRIMARY AND SECONDARY BUSES AT 33MH 17.6 POWER CONSUMPTION ........................................................................................................ 103 18 272-PIN PBGA PACKAGE FIGURE ........................................................................................ 104 18.1 PART NUMBER ORDERING INFORMATION ...................................................................... 104 APPENDIX A: PI7C7300A EVALUATION BOARD USER’S MANUAL....................................... 105 FREQUENTLY ASKED QUESTIONS ................................................................................................. 107 LIST OF TABLES T 4-1 PCI TRANSACTIONS .............................................................................................................. 21 ABLE T 4-2 WRITE TRANSACTION FORWARDING .............................................................................. 23 ABLE T 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ...
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... ABLE T 16-2 JTAG BOUNDARY REGISTER ORDER .............................................................................. 98 ABLE LIST OF FIGURES F 9-1 SECONDARY ARBITER EXAMPLE..................................................................................... 65 IGURE F 16-1 TEST ACCESS PORT BLOCK DIAGRAM.......................................................................... 95 IGURE F 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS ................................................. 102 IGURE F 18-1 272-PIN PBGA PACKAGE ................................................................................................. 104 IGURE 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 9 OF 109 09/25/03 Revision 1.09 PI7C7300A ...
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... PCI Bus to communicate even while the Primary Bus is busy. In addition, the Secondary Buses have load balancing capability, allowing faster devices to be isolated away from slower devices. Among the other features supported by the PI7C7300A are: support for devices on the Secondary Buses, Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support and Dual Addressing Cycle ...
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... BLOCK DIAGRAM 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 12 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... P_TRDY# is asserted. Data is transferred on rising W16, Y16, W17, clock edges when both P_IRDY# and P_TRDY# are Y17, U18, W18, asserted. During bus idle, PI7C7300A drives P_AD to Y18, U19, W19, a valid logic level when P_GNT# is asserted. Y19, U20, V20, Y20, T17, R17 ...
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... Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. Primary Request (Active LOW). This is asserted by PI7C7300A to indicate that it wants to start a transaction on the primary bus. PI7C7300A de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW). ...
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... Type Description V18 PI Primary Interface 66MHz Operation. This input is used to specify if PI7C7300A is capable of running at 66MHz. For 66MHz operation on the Primary bus, this signal should be pulled “HIGH”. For 33MHz operation on the Primary bus, this signal should be pulled “LOW”. S1_M66EN and S2_M66EN will both need to be “ ...
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... S2_EN is inactive, secondary bus PCI S1 or PCI S2 will be asynchronously tri-stated. Secondary Interface 66MHz Operation. This input is used to specify if PI7C7300A is capable of running at 66MHz on the secondary side. When HIGH, the bus may run at 66MHz. When LOW, the bus may only run at 33MHz. ...
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... If HS_EN is LOW, pin is S2_REQ#[7 Hot Swap Enable. To enable Hot Swap Friendly support, this signal should be pulled HIGH. Page 17 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 09/25/03 Revision 1.09 ...
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... Pin # Type Description V2 PIU Test Clock. Used to clock state information and data into and out of the PI7C7300A during boundary scan. W1 PIU Test Mode Select. Used to control the state of the Test Access Port controller. V3 PTS Test Data Output. When SCAN_EN is HIGH used (in conjunction with TCK) to shift data out of the Test Access Port (TAP serial bit stream ...
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... K3 S2_REQ#[0] PIU K9 VSS - K11 VSS - K17 S1_CBE[1] PB K19 VSS - L1 S2_GNT#[ S2_CLKOUT[2] PTS L9 VSS - Page 19 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Pin # Name Type A18 S1_CLKOUT[1] PTS A20 VSS - B2 S2_IRDY# PSTS B4 S2_PAR PB B6 S2_AD[11 VDD - B10 S1_RESET# ...
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... Y3 PLL_TM PI Y5 P_RESET P_AD[31 P_AD[25] PB Y11 P_AD[21] PB Y13 VSS - Y15 P_PERR# PSTS Page 20 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Pin # Name Type L12 VSS - L18 S1_AD[13] PB L20 S1_AD[15 S2_REQ#[3] PIU M4 S2_CLKOUT[3] PTS M10 VSS ...
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... Table 4-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7300A initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7300A responds to transactions as a target, on the primary (P) and secondary (S1, S2) buses. Table 4-1 PCI TRANSACTIONS ...
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... P_CBE[3:0]. PI7C7300A supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C7300A automatically disconnects the transaction after the first data transfer. ...
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... The posted write data buffer fills up. When one of the last two events occurs, the PI7C7300A returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, PI7C7300A asserts its request on the target bus ...
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... DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C7300A can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C7300A and the initiator stalls, PI7C7300A will signal the last data phase for the current transaction at the target bus if the queue empties ...
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... When a write transaction is first detected on the initiator bus, and PI7C7300A forwards delayed transaction, PI7C7300A claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, PI7C7300A samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, PI7C7300A also samples the first data DWORD, byte enable bits, and data parity ...
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... However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C7300A forces all byte enable bits to be turned on for all data phases. 3-PORT PCI-TO-PCI BRIDGE ...
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... PI7C7300A stops pre-fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C7300A finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered ...
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... PI7C7300A drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C7300A receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered ...
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... For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C7300A can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD transferred during a delayed read transaction depends on the conditions given in Table 4-5 (assuming no disconnect is received from the target) ...
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... PI7C7300A has the capability to post multiple delayed read requests maximum of four in each direction initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted already contained in the delayed transaction queue. ...
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... PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C7300A performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus ...
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... Fh 10h – 1Eh 1Fh PI7C7300A can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted ...
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... Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the down-stream direction. PI7C7300A initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: ! The lowest two address bits on AD[1:0] are equal to 01b ...
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... The bus command on CBE configuration write command. When PI7C7300A initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are for-warded unchanged. Devices that use special cycles ignore the address and decode only the bus command ...
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... MASTER TERMINATION INITIATED BY PI7C7300A PI7C7300A initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of PI7C7300A’s assertion of FRAME# on the target bus initiator, PI7C7300A terminates a transaction when the following conditions are met: ! During a delayed write transaction, a single DWORD is delivered. ...
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... For delayed read and write transactions, PI7C7300A is able to reflect the master abort condition back to the initiator. When PI7C7300A detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7300A does not respond to the transaction with DEVSEL# which induces the master abort condition back to the initiator ...
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... DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C7300A will use the memory write command to deliver the rest of the write data because an incomplete cache line will be transferred in the subsequent write transaction attempt ...
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... Target Disconnect Target Abort After PI7C7300A makes 2 the target bus, PI7C7300A asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h) ...
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... The delayed transaction queue is full, and the transaction cannot be queued transaction with the same address and command has been queued locked sequence is being propagated across PI7C7300A, and the write transaction is not a locked transaction. ! The target bus is locked and the write transaction is a locked transaction. ...
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... PI7C7300A returns a target abort to an initiator when one of the following conditions is met: ! PI7C7300A is returning a target abort from the intended target. When PI7C7300A returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. 4.10 CONCURRENT MODE OPERATION The Bridge can be configured to run in concurrent operation ...
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... I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master- enable bit is not set, PI7C7300A ignores all I/O and memory transactions initiated on the secondary bus. The master-enable bit also allows upstream forwarding of memory transactions set ...
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... ISA mode modifies the response of PI7C7300A inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of PI7C7300A when the transaction falls inside the address range defined by the I/O base and limit address registers, and only ...
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... All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of PI7C7300A can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary ...
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... The prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C7300A uses to determine when to for- ward memory commands. PI7C7300A forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range ...
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... PI7C7300A does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism). ...
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... I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7300A behaves in the same way as if only the VGA mode bit were set. ...
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... PI7C7300A does not combine separate write transactions into a single write transaction—this optimization is best implemented in the originating master. ! PI7C7300A does not merge bytes on separate masked write transactions to the same DWORD address—this optimization is also best implemented in the originating master. ! PI7C7300A does not collapse sequential write transactions to the same address into a single write transaction— ...
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... The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C7300A and must also be true for other bus agents. Otherwise, a deadlock can occur. ! PI7C7300A accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C7300A ...
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... In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C7300A as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator ...
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... When PI7C7300A detects an address parity error on the primary interface, the following events occur the parity error response bit is set in the command register, PI7C7300A does not claim the transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7300A proceeds normally and accepts the transaction directed to or across PI7C7300A ...
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... If the parity error response bit is set in the bridge control register, PI7C7300A does not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7300A proceeds normally and accepts transaction directed to or across PI7C7300A ...
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... PI7C7300A completes the transaction normally. PI7C7300A returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs assumed that the initiator takes responsibility for handling a parity error condition ...
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... When PI7C7300A detects a parity error on the write data for the initial delayed write request transaction, the following events occur the parity-error-response bit corresponding to the initiator bus is set, PI7C7300A asserts TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect ...
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... Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7300A has write status to return, the following events occur: ! PI7C7300A first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two cycles later, if the secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch) ...
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... PI7C7300A asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. ! PI7C7300A sets the parity error detected bit in the status register of the secondary interface. ! PI7C7300A captures and forwards the bad parity condition to the primary bus. ...
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... PI7C7300A to data parity errors according to the status bits that PI7C7300A sets and the signals that it asserts. Table 7-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C7300A detects a parity error on the primary interface. Table 7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT ...
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... Delayed Write X = don’t care Table 7-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C7300A detects a parity error on the secondary interface. Table 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT Secondary ...
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... X= don’t care Table 7-5 shows assertion of P_PERR#. This signal is set under the following conditions: ! PI7C7300A is either the target of a write transaction or the initiator of a read transaction on the primary bus. ! The parity-error-response bit must be set in the command register of primary interface. ! ...
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... PI7C7300A has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted on a downstream posted write transaction. ! PI7C7300A did not detect the parity error as a target of the posted write transaction. ! The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set ...
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... Whenever assertion of P_SERR# is discussed in this document assumed that the following conditions apply: ! For PI7C7300A to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. ! Whenever PI7C7300A asserts P_SERR#, PI7C7300A must also set the signaled system error bit in the status register. ...
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... When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target’s bus. When PI7C7300A detects on the primary bus, an initial locked transaction intended for a target on the secondary bus, PI7C7300A samples the address, transaction type, byte enable bits, and parity, as described in Section 4 ...
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... I/O Write induces master abort - Memory Write induces master abort When PI7C7300A receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. PI7C7300A resumes forwarding unlocked transactions in both directions ...
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... Section 4.8). Normal forwarding of unlocked posted and delayed transactions is resumed. When PI7C7300A receives a target abort or a master abort in response to a locked posted write transaction, PI7C7300A cannot pass back that status to the initiator. PI7C7300A asserts SERR# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register ...
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... PCI clock cycle. When P_GNT# is asserted to PI7C7300A when P_REQ# is not asserted, PI7C7300A parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at PI7C7300A and PI7C7300A has a transaction to initiate on the primary bus, PI7C7300A starts the transaction if P_GNT# was asserted during the previous cycle ...
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... Error! Reference source not found. shows an example of an internal arbiter where four masters, including PI7C7300A, are in the high priority group, and five masters are in the low priority group. Using this example, if all requests are always asserted, the highest priority rotates among ...
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... PI7C7300A parks the primary bus only when P_GNT# is asserted, P_REQ# is de- asserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, PI7C7300A 3- states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7300A is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C7300A can start the transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted ...
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... If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C7300A keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, PI7C7300A parks the secondary bus at itself until transactions start occurring on the secondary bus ...
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... RESET This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 12.1 PRIMARY INTERFACE RESET PI7C7300A has a reset input, P_RESET#. When P_RESET# is asserted, the following events occur: ! PI7C7300A immediately 3-states all primary and secondary PCI interface signals. ! PI7C7300A performs a chip reset. ...
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... Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. When S1_RESET# or S2_RESET# is asserted by means of the secondary reset bit, PI7C7300A remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface. 13 SUPPORTED COMMANDS The PCI command set is given below for the primary and secondary interfaces ...
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... CONFIGURATION REGISTERS As PI7C7300A supports two secondary interfaces, it has two sets of configuration registers that are almost identical and accessed through different function numbers. PCI configuration defines a 64-byte space (configuration header) to define various attributes of the PCI-to-PCI Bridge as shown below. There are two configuration registers: ...
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... Secondary Bus 2 interfaces respectively. The configuration for the Primary interface is implemented through Configuration Register 1. Page 71 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 09/25/03 Revision 1.09 ...
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... Primary Successful Memory Write Counter Reserved Slot Number Next Pointer Reserved Next Pointer Reserved Type Description R/O Identifies Pericom as vendor of this device. Hardwired as 12D8h. Page 72 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 7-0 Address Vendor ID 00h Command 04h Revision ID 08h Cache Line Size ...
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... Controls ability to operate as a bus master on the primary interface 0: do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on secondary 1 interface R/W 1: enables PI7C7300A to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface Reset special cycles defined. ...
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... Controls response to parity errors 0: PI7C7300A may ignore any parity errors that it detects and continue normal operation R/W 1: PI7C7300A must take its normal action when a parity error is detected Reset to 0 Controls the ability to perform address / data stepping 0: disable address/data stepping (affects primary and secondary) ...
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... Reset to 0 Type Description R/W This register sets the value for the Master Latency Timer which starts counting when the master asserts FRAME#. Reset to 0 Page 75 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... Indicates the number of the PCI bus with the highest number that is subordinate to the bridge. The value is set in software during configuration. Reset to 0 Type Description R/W Designated in units of PCI bus clocks. Latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. Reset to 0 Page 76 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... R/WC Reset to 0 DEVSEL# timing (medium decoding) 00: fast DEVSEL# decoding 01: medium DEVSEL# decoding R/O 10: slow DEVSEL# decoding 11: reserved Reset to 01 Set to 1 (by a target device) whenever a target abort cycle occurs on its secondary (S1 or S2) interface R/WC Reset to 0 Page 77 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh. Type Description R/O Indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing Reset to 1 Page 78 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... Reset to 0 Type Description R/W Defines the upper 16-bits of a 32-bit bottom address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0 Page 79 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... I/O base and I/O limit registers that are in the first 64KB of I/O space that address the last 768 bytes in each 1KB block. Secondary I/O transactions are forwarded upstream if the address falls within the last 768 bytes in each 1KB block Reset to 0 Page 80 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... Reserved. Returns 0 when read. Reset to 0 R/W Controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4KB aligned address boundary 1: memory write disconnects at cache line aligned address boundary Reset to 0 R/O Reserved. Returns 0 when read. Reset to 0. Page 81 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... The bits are used for chip test only. S2 00: all bits are exercised 01: byte 1 is exercised 10: byte 2 is exercised 11: byte 3 is exercised Reset to 0 15:11 Reserved R/O Reserved. Returns 0 when read. Reset to 0. Page 82 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 09/25/03 Revision 1.09 ...
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... Reset Upstream memory is prefetchable at Primary R/W 1: Upstream memory is not prefetchable at Primary Reset to 0 R/O Reserved. Returns 0 when read. Reset to 0 Type Description Hot Swap time slot (15K PCI clocks) R/W Reset to 0003A98h Page 83 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... Reset to 1 Controls upstream memory base address. R/W Reset to 00000000h Type Description 0: 32 bit addressing R bit addressing Reset to 1 Controls upstream memory limit address. R/W Reset to 000FFFFFh Type Description Defines bits [63:32] of the upstream memory base R/W Reset to 0 Page 84 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... Reset to 0 Type Description R/O Reserved. Returns 0 when read. Reset to 0 Controls PI7C7300A’s ability to assert P_SERR# when it is unable to transfer any read data from the target after 2 0: P_SERR# is asserted if this event occurs and the SERR# enable bit R/W in the command register is set. ...
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... Reserved 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Type Description Controls PI7C7300A’s ability to assert P_SERR# when it is unable to transfer any read data from the target after 2 0: P_SERR# is asserted if this event occurs and the SERR# enable bit R/W in the command register is set ...
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... Controls PI7C7300A’s ability to enable long requests for lock cycles 0: normal lock operation Enable Long 9 R/W Request 1: enable long request for lock cycle Reset to 0 Control’s PI7C7300A’s ability to enable hold requests longer. Enable 0: internal master will release REQ_L after FRAME_L Secondary To assertion 10 R/W ...
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... FIFO or until terminated by target Reset to 1 R/O Reserved. Returns 0 when read. Reset to 0. Type Description Holds the maximum number of PCI clocks that PI7C7300A will wait for initiator to retry the same cycle before reporting timeout. Master R/W 15 timeout occurs after 2 PCI clocks. ...
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... Reset to 0 Type Description Stores the successful I/O read count on Primary and is updated when the sampling timer is active. R/W Reset to 0 Type Description Stores the successful I/O write count on Primary and is updated when the sampling timer is active. R/W Reset to 0 Page 89 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... Slot Identification (SI) 05h: Message Signaled Interrupts (MSI) 06h: Compact PCI Hot Swap (CHS) 07h – 255h: Reserved Reset to 04h Type Description Reset to 1100 0000: next pointer (C0h if HS_EN is 1) R/O 0000 0000: next pointer (00h if HS_EN is 0) Page 90 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... Compact PCI Hot Swap (CHS) 07h – 255h: Reserved Reset to 06h Type Description R/O 00: End of pointer (00h). Type Description R/O Not used. Returns 0 when read. Reset Mask ENUM# signal R/W 1: Enable ENUM# signal R/O Not used. Returns 0 when read. Reset to 0 Page 91 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... ENUM# not asserted Reset to 0 R/O Reserved. Returns 0 when read. Reset to 0 Target Response Target on Primary PI7C7300A does not respond. It detects this situation by decoding the address as well as monitoring the P_DEVSEL# for other fast and medium devices on the Primary Port. Target on Secondary PI7C7300A asserts P_DEVSEL#, terminates the cycle normally able to be posted, otherwise return with a retry ...
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... ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) 15.3.1 MASTER ABORT Master abort indicates that when PI7C7300A acts as a master and receives no response (i.e., no target asserts DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the bridge deasserts FRAME# and then deasserts IRDY#. 15.3.2 PARITY AND ERROR REPORTING Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, S1_PAR, and S2_PAR signals. Parity should be even ( even number of‘ ...
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... Master Abort. 15.3.4 SECONDARY IDSEL MAPPING When PI7C7300A detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11 device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7300A. ...
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... Figure 16-1 TEST ACCESS PORT BLOCK DIAGRAM 16.1.1 TAP PINS The PI7C7300A’s TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are described in Table 16-1. The TAP pins provide access to the instruction register and the test data registers ...
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... TDI shifts, and becomes active on the falling edge of TCK. 16.2 BOUNDARY-SCAN INSTRUCTION SET The PI7C7300A supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). The table shown below lists the PI7C7300A’s boundary-scan instruction codes. The “reserved” code should not be used. Instruction Code (binary) 0000 ...
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... The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 16-2 shows the bit order of the PI7C7300A boundary-scan register. All table cells that contain “Control” select the direction of bi-directional pins or high-impedance output pins. When a “0” is loaded into the control cell, the associated pin(s) are high- impedance or selected as input ...
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... P_AD[1] control 101 P_AD[3] bidir 102 P_AD[3] control 103 P_AD[4] bidir 104 P_AD[4] control 105 S1_AD[0] Page 98 OF 109 PI7C7300A Type control bidir control input output control bidir control bidir control bidir control bidir control bidir control bidir control ...
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... S1_CBE[2] control 165 S1_AD[19] bidir 166 S1_AD[19] control 167 S1_CBE[3] bidir 168 S1_CBE[3] control Page 99 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Order Pin Names Type 106 S1_AD[0] control 107 S1_AD[1] bidir 108 S1_AD[1] control 109 S1_AD[2] ...
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... S2_REQ#[4] control 311 S2_REQ#[5] bidir 312 S2_GNT#[5] control 313 S2_GNT#[6] bidir 314 S2_REQ#[6] control bidir control bidir control Page 100 OF 109 PI7C7300A Type bidir control bidir control bidir control Input bidir control bidir control bidir control bidir control bidir control bidir ...
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... < V < 0. -500µA out 1500µA out V – 0 -500µA out 1500µA out 5 Page 101 OF 109 PI7C7300A -65°C to 150°C -40°C to 85°C -0.3V to 3.6V -0.5V to 3.6V Max. Units Notes ...
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... S2_SERR#, S2_FRAME#, S2_IRDY#, S2_TRDY#, S2_LOCK#, S2_DEVSEL#, and S2_STOP#. 4. REQ# signals have a setup of 10 and GNT# signals have a setup of 12. 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 66 MHz Min. 1,2,3 3 1,2,3 5 1,2 0 1,2,3 2 1,2,3 2 1,2 2 1,2 - Page 102 OF 109 PI7C7300A 33 MHz Max. Min. Max. Units - 10 ...
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... Note: Typical values are at VCC = 3.3V 25°C, and all three ports running at 66MHz. 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Condition 20pF load 20pF load Condition 20pF load 20pF load Typical 2178 660 Page 103 OF 109 PI7C7300A Min. Max. Units 0 250 ps 0 250 3.3 4.9 3.3 4.9 ...
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... Figure 18-1 272-PIN PBGA PACKAGE TOP Thermal Characteristics can be found on the web: 18.1 PART NUMBER ORDERING INFORMATION Part Number PI7C7300ANA 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION BOTTOM http://www.pericom.com/packaging/mechanicals.php Pin – Package Temperature 272 – PBGA -40°C to 85°C Page 104 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
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... APPENDIX A: PI7C7300A EVALUATION BOARD USER’S MANUAL GENERAL INFORMATION 1. Please make sure you have included with your PI7C7300A evaluation board, the five-page schematic and the preliminary specification for the PI7C7300A. 2. Check all jumpers for proper settings: Pin Name Jumper S_CFN# S1_EN ...
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... GENERAL INFORMATION (continued) 6. Turn on the power for the system. Your OS should already have drivers for the PI7C7300A evaluation board. In Win9X, Plug and Play should detect the device as a PCI-to-PCI bridge. The system may prompt you for the Win9X CD for the drivers. The OS will detect two PCI-to-PCI bridges as the PI7C7300A has two secondary PCI buses ...
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... AD21 AD21 CBE2 IRDY LOCK AD20 AD20 FRAME DVSEL PERR AD22 AD22 AD24 IRDY STOP Page 107 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PAR AD14 AD11 CBE0 AD6 CBE1 AD13 AD10 AD8 AD4 SERR AD15 ...
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... What clock frequency combinations does the PI7C7300A support? Primary 66MHz 66MHz 66MHz 66MHz 33MHz 50MHz 50MHz 50MHz 50MHz 25MHz ! How are the JTAG signals being connected? The JTAG signals consist of TRST#, TCK, TMS, TDI, and TDO. All the mentioned signals have weak internal pull-up connections ...
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... PCI-TO-PCI BRIDGE ADVANCE INFORMATION NOTES: Page 109 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...