PI7C7300 Pericom Semiconductor Corporation, PI7C7300 Datasheet - Page 57

• Manufacturer Part Number: PI7C7300
• Description: 3-PORT PCI-to-PCI BRIDGE
• Manufacturer: Pericom Semiconductor Corporation

Table 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT
Table 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT
X = don’t care
Table 7-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C7300A detects a
parity error on the secondary interface.
X = don’t care
Table 7-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
!
!
!
X = don’t care
Primary Detected
Parity Error Bit
0
Secondary
Detected Parity
Error Bit
0
1
0
0
0
0
0
1
0
0
0
1
Primary Data
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
0
PI7C7300A must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR# signal is detected asserted or a parity error is detected on the primary
bus.
Transaction Type
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Direction
Direction
Direction
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
3-PORT PCI-TO-PCI BRIDGE
Bus Where Error
Was Detected
Secondary
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
ADVANCE INFORMATION
09/25/03 Revision 1.09
Primary/
Secondary Parity
Error Response
Bits
x / x
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
Primary /
Secondary Parity
Error Response
Bits
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
PI7C7300A