PI7C7300 Pericom Semiconductor Corporation, PI7C7300 Datasheet - Page 59

• Manufacturer Part Number: PI7C7300
• Description: 3-PORT PCI-to-PCI BRIDGE
• Manufacturer: Pericom Semiconductor Corporation

Table 7-6 ASSERTION OF S_PERR#
Table 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
X = don’t care
2
Table 7-6 shows assertion of S_PERR# that is set under the following conditions:
!
!
!
X = don’t care
2
the initiator (primary) bus.
Table 7-7 shows assertion of P_SERR#. This signal is set under the following conditions:
!
!
!
!
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (secondary) bus but not on
0
1
1
S_PERR#
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
0
P_SERR#
2
2
PI7C7300A is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C7300A detects a data parity error on the secondary bus or detects P_PERR#
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
PI7C7300A has detected P_PERR# asserted on an upstream posted write transaction
or S_PERR# asserted on a downstream posted write transaction.
PI7C7300A did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response
bit on the bridge control register must both be set.
The SERR# enable bit must be set in the command register.
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
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Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
3-PORT PCI-TO-PCI BRIDGE
Secondary
Primary
Secondary
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
ADVANCE INFORMATION
09/25/03 Revision 1.09
1 / 1
x / x
x / x
Primary/
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
Primary /
Secondary Parity
Error Response
Bits
PI7C7300A