74LVC2G126 Philips Semiconductors, 74LVC2G126 Datasheet - Page 2

• Manufacturer Part Number: 74LVC2G126
• Description: Dual bus buffer/line driver; 3-state
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2004 Sep 22
t
C
C
PHL
SYMBOL
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
I
PD
Dual bus buffer/line driver; 3-state
24 mA output drive (V
P
f
f
C
V
N = total load switching outputs;
i
o
/t
D
CC
PD
= input frequency in MHz;
L
(C
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay inputs nA to output nY V
input capacitance
power dissipation capacitance per buffer output enabled; notes 1 and 2
2
V
CC
= 25 C.
f
o
2
) = sum of outputs.
I
f
= GND to V
i
CC
N + (C
PARAMETER
= 3.0 V)
CC
L
.
V
CC
2
f
o
) where:
V
V
V
V
output disabled; notes 1 and 2
CC
CC
CC
CC
CC
2
DESCRIPTION
The 74LVC2G126 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
These feature allows the use of these devices as
translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using I
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G126 provides a dual non-inverting buffer/line
driver with 3-state output. The 3-state output is controlled
by the output enable input (pin nOE). A LOW-level at
pin nOE causes the output to assume a high-impedance
OFF-state. Schmitt-trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
= 1.8 V; C
= 2.5 V; C
= 2.7 V; C
= 3.3 V; C
= 5.0 V; C
D
in W).
CONDITIONS
L
L
L
L
L
= 30 pF; R
= 30 pF; R
= 50 pF; R
= 50 pF; R
= 50 pF; R
off
. The I
L
L
L
L
L
= 1 k
= 500
= 500
= 500
= 500
off
circuitry disables the output,
Product specification
74LVC2G126
3.9
2.6
2.8
2.4
1.9
2
17
5
TYPICAL
ns
ns
ns
ns
ns
pF
pF
pF
UNIT