PCF8576C Philips Semiconductors, PCF8576C Datasheet - Page 15

• Manufacturer Part Number: PCF8576C
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: Philips Semiconductors

Philips Semiconductors
6.5
6.5.1
The internal logic and the LCD drive signals of the
PCF8576C are timed either by the built-in oscillator or from
an external clock. When the internal oscillator is used,
OSC (pin 6) should be connected to V
event, the output from CLK (pin 4) provides the clock
signal for cascaded PCF8566s or PCF8576Cs in the
system.
Note that the PCF8576C is backwards compatible with the
PCF8576. Where resistor R
internal oscillator is selected.
6.5.2
The condition for external clock is made by tying OSC
(pin 6) to V
clock input.
The clock frequency (f
frequency and the maximum rate for data reception from
the I
maximum data rate of 100 kHz, f
above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6
The timing of the PCF8576C organizes the internal data
flow of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal SYNC
maintains the correct timing relationship between the
PCF8576Cs in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 3). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to pin 4
when external clock is used.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I
1998 Jul 30
Universal LCD driver for low multiplex
rates
2
C-bus. To allow I
Oscillator
Timing
I
E
NTERNAL CLOCK
XTERNAL CLOCK
DD
; CLK (pin 4) then becomes the external
clk
2
C-bus transmissions at their
) determines the LCD frame
osc
to V
clk
should be chosen to be
SS
2
C-bus.
is present, the
SS
(pin 11). In this
15
When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I
6.7
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
6.8
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
6.9
The LCD drive section includes 40 segment outputs
S0 to S39 (pins 17 to 56) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with data resident in the display latch. When
less than 40 segment outputs are required the unused
segment outputs should be left open-circuit.
6.10
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode BP0
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
Display latch
Shift register
Segment outputs
Backplane outputs
2
C-bus but no data loss occurs.
Product specification
PCF8576C