PCF8576C Philips Semiconductors, PCF8576C Datasheet - Page 25

• Manufacturer Part Number: PCF8576C
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 10 Load data pointer option 1
Table 11 Device select option 1
Table 12 Bank select option 1
Table 13 Bank select option 2
7.9
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8576C and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
7.10
In large display configurations, up to 16 PCF8576Cs can
be distinguished on the same I
hardware subaddress (A0, A1 and A2) and the
programmable I
cascaded PCF8576Cs are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8576Cs of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (Fig.18).
1998 Jul 30
6 bit binary value of 0 to 39
3 bit binary value of 0 to 7
RAM bit 0
RAM bit 2
RAM bit 0
RAM bit 2
Universal LCD driver for low multiplex
rates
STATIC
STATIC
Display controller
Cascaded operation
DESCRIPTION
DESCRIPTION
2
C-bus slave address (SA0). When
RAM bits 0 and 1
RAM bits 2 and 3
RAM bits 0 and 1
RAM bits 2 and 3
1 : 2 MUX
1 : 2 MUX
2
P5 P4 P3 P2 P1 P0
C-bus by using the 3-bit
A0
BITS
BITS
A1
BIT O
BIT I
0
1
0
1
A2
25
Table 14 Blink option 1
Table 15 Blink option 2
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8576Cs. This
synchronization is guaranteed after the power-on reset.
The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8576Cs with differing SA0
levels are cascaded). SYNC is organized as an
input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor.
A PCF8576C asserts the SYNC line at the onset of its last
active backplane signal and monitors the SYNC line at all
other times. Should synchronization in the cascade be
lost, it will be restored by the first PCF8675C to assert
SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for the various drive
modes of the PCF8576C are shown in Fig.19.
For single plane wiring of packaged PCF8576Cs and
chip-on-glass cascading, see Chapter “Application
information”.
Off
2 Hz
1 Hz
0.5 Hz
Normal blinking
Alternation blinking
BLINK FREQUENCY
BLINK MODE
BF1
0
0
1
1
Product specification
PCF8576C
BIT A
BITS
0
1
BF0
1
0
0
1