TC7109 TelCom, TC7109 Datasheet
TC7109
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TC7109 Summary of contents
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... V – REF OUT TELCOM SEMICONDUCTOR, INC. GENERAL DESCRIPTION The TC7109A is a 12-bit plus sign, CMOS low-power analog-to-digital converter (ADC). Only eight passive com- ponents and a crystal are required to form a complete dual-slope integrating ADC. The improved V tures that make it an attractive per-channel alternative to analog multiplexing for many data acquisition applica- tions ...
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... GND may cause destructive device latch- up. Therefore recommended that inputs from sources other than the same power supply should not be applied to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be activated first. ...
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... Test Conditions Min + Referenced – 2.4 + Between V and Ref Out + 25 k Between V and Ref Out — + TC7109 100 A 3.5 OUT TC7109A 700 A OUT Pins 3–16, 18, 19 1.6 mA — OUT Pins 3–16 High Impedance — + Pins 18, 19 –3V — ...
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... POL TC7109A TC7109 B 12 (CPL, IJL MJL (PDIP) (CerDIP TEST LBEN 22 HBEN ...
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... P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109/A PIN DESCRIPTION 40-Pin PDIP Pin Number Symbol 1 GND 2 STATUS 3 POL TEST 18 LBEN 19 HBEN 20 CE/LOAD 21 MODE 22 OSC IN ...
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... OUTPUT * NOTE: For lowest power consumption, TBR1–TBR8 inputs should have 100k Figure 1. TC7109A UART Interface (Send Any Word to UART to Transmit Latest Result) 3-96 ANALOG-TO-DIGITAL CONVERTERS Description Input — Used in handshake mode to indicate ability of an external device to accept data. Connect not used. ...
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... DETAILED DESCRIPTION (All Pin Designations Refer to 40-Pin DIP) Analog Section The functional diagram shows a block diagram of the analog section of the TC7109A. The circuit will perform conversions at a rate determined by the clock frequency (8192 clock periods per cycle), when the RUN/HOLD input + is left open or connected to V ...
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... The ZI phase only occurs following an overrange and lasts for a maximum of 1024 clock periods. Differential Input The TC7109A has been optimized for operation with analog common near digital ground. With +5V and –5V power supplies, a full 4V full-scale integrator swing maxi- mizes the analog section's performance. ...
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... OSCILLATOR CONTROL AND CLOCK LOGIC CIRCUITRY RUN/ OSC OSC OSC BUFF MODE IN OUT SEL OSC HOLD OUT Figure 4. Digital Section TC7109 TC7109A ZI AZ ZERO INTEGRATOR PHASE FORCES INTEGRATOR OUTPUT LBEN 19 HBEN ...
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... CE/LOAD AS INPUT HBEN AS INPUT LBEN AS INPUT HIGH-BYTE DATA LOW-BYTE DATA Figure 6. Table 1. TC7109A Direct Mode Timing Requirements Symbol Description t Byte Enable Width BEA t Data Access Time DAB From Byte Enable t Data Hold Time DHB ...
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... The MODE input controls the handshake mode. When the MODE input is held HIGH, the TC7109A enters the handshake mode after new data has been stored in the output latches at the end of every conversion performed (see Figures 7 and 8) ...
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... TC7109A Handshake With SEND INPUT Held Positive ZERO CROSSING OCCURS ZERO CROSSING DETECTED SEND SEND SENSED SENSED DATA VALID = THREE-STATE HIGH IMPEDANCE = DON'T CARE TC7109A Handshake — Typical UART Interface Timing 12-BIT P-COMPATIBLE TERMINATES UART MODE MODE LOW, NOT IN HANDSHAKE MODE DISABLES OUTPUTS ...
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... SEND SENSED SENSED DATA VALID = THREE-STATE HIGH IMPEDANCE Figure 9. TC7109A Handshake Triggered by MODE Input a fixed 58 divider circuit between the BUFFERED OSCIL- LATOR OUTPUT and the internal clock. A 3.58 MHz TV crystal gives a division ratio providing an integration time given by (2048 clock periods) The error is less than 1% from two 60 Hz periods ...
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... R INT 5V supplies and Auto-Zero Capacitor As the auto-zero capacitor is made large, the system noise is reduced. Since the TC7109A incorporates a zero integrator cycle, the size of the auto-zero capacitor does not affect overload recovery. The optimal value of the auto-zero capacitor is between 2 and 4 times 0.33 F. ...
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... Reference Sources A major factor in the absolute accuracy of the ADC is the stability of the reference voltage. The 12-bit resolution of the TC7109A is one part in 4096, or 244 ppm. Thus, for the on- board reference temperature coefficient of 70 ppm temperature difference will introduce a one-bit abso- lute error ...
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... GND OR CHIP SELECT 2 CONVERTER SELECT GND MODE CE/LOAD B9–B12 POL, OR TC7109A B1–B8 ANALOG IN +5V RUN/HOLD HBEN LBEN Figure 13. Three-Stating Several TC7109A Small Bus 12-BIT P-COMPATIBLE CHIP SELECT C. GND MODE CE/LOAD B9–B12 POL TC7109A B1–B8 ANALOG IN RUN/HOLD CONVERT HBEN LBEN ...
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... CONTROL BUS DATA BUS RD WR D7–D0 A0– PA5–PA0 PC6 8255 8 PB7–PB0 STB A PC4 PC6 1 F 10k +5V (SEE TEXT) TC7109 TC7109A 87C48 8008, 8080, 8085, 8048, ETC. 87C48 8008, 8080, 8085, 8048, ETC. INTR A INTR 3-107 ...
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... A15 CONTROL BUS * RD DATA BUS HBEN LBEN B9–B12 6 POL, OR B1–B8 8 TC7109A CE/LOAD MODE RUN/HOLD * MEMR or IOR for 8080/8228 system. GND +5V Figure 17. TC7109A Direct Interface to 8080/8085 12-BIT P-COMPATIBLE MC6800 MCS650X DATA CONTROL BUS BUS BUS 8008, 8080, 8085 TELCOM SEMICONDUCTOR, INC. OR ...
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... IN B1–B8 TC7109A CE/LOAD B9–B12 POL, OR ANALOG B1–B8 IN TC7109A CE/LOAD SEND RUN/HOLD MODE Figure 19. TC7109A Handshake Interface to MCS-48, -80, -85 Microcomputers TELCOM SEMICONDUCTOR, INC HBEN 74C42 A0–A2 LBEN A15–A10 74C30 R/W, VMA ADDRESS Figure 18. TC7109A Direct Interface to MC6800 Bus ADDRESS BUS ...
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... CE/LOAD to drive the 8255 strobe. The internal control register of the PPI should be set in MODE 1 for the port used. If the 8255 IBF flag is LOW and the TC7109A is in handshake mode, the next word will be strobed into the port. The strobe will cause IBF to go HIGH (SEND goes LOW), which will keep the enabled byte outputs active ...
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... RUN/HOLD HBEN LBEN Handshake Interface for Multiplexed Converters 0.1/t Figure 22. Normal Mode Rejection of Dual-Slope Converter as a TC7109 TC7109A MODE CE/ SEND LOAD B9–B12 POL, OR ANALOG IN B1–B8 TC7109A +5V RUN/HOLD HBEN LBEN t = MEASUREMENT PERIOD 1/t INPUT FREQUENCY Function of Frequency + 10/t ...