TC7109 TelCom, TC7109 Datasheet - Page 10

• Manufacturer Part Number: TC7109
• Description: 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: TelCom

sion time. If RUN/HOLD goes LOW any time after zero
crossing in the deintegrate mode, the circuit will jump to
auto-zero and eliminate that portion of time normally spent
in deintegrate.
complete with minimum time in deintegrate. It will stay in
auto-zero for the minimum time and wait in auto-zero for a
HIGH at the RUN/HOLD input. As shown in Figure 5, the
STATUS output will go HIGH 7 clock periods after RUN/
HOLD is changed to HIGH, and the converter will begin the
integrate phase of the next conversion.
terface. The converter may be held at idle in auto-zero with
RUN/HOLD LOW. The conversion is started when RUN/
HOLD goes HIGH, and the new data is valid when the
STATUS output goes LOW (or is transferred to the UART;
see "Handshake Mode"). RUN/HOLD may now go LOW,
terminating deintegrate and ensuring a minimum auto-zero
time before stopping to wait for the next conversion. Conver-
sion time can be minimized by ensuring RUN/HOLD goes
LOW during deintegrate, after zero crossing, and goes
HIGH after the hold point is reached. The required activity on
the RUN/HOLD input can be provided by connecting it to the
buffered oscillator output. In this mode, the input value
measured determines the conversion time.
Direct Mode
9 through 12, polarity and overrange high-order bytes) are
accessible under control of the byte and chip enable termi-
nals as inputs with the MODE pin at a LOW level. These
three inputs are all active LOW. Internal pull-up resistors are
provided for an inactive HIGH level when left open. When
chip enable is LOW, a byte-enable input LOW will allow the
outputs of the byte to become active. A variety of parallel
3-100
TC7109
TC7109A
The RUN/HOLD input may be used to shorten conver-
If RUN/HOLD stays or goes LOW, the conversion will
The RUN/HOLD input allows controlled conversion in-
The data outputs (bits 1 through 8, low-order bytes; bits
INTEGRATOR OUTPUT
INTERNAL CLOCK
INTERNAL LATCH
RUN/HOLD INPUT
STATUS OUTPUT
*
NOTE:
RUN/HOLD input is ignored until end of auto-zero phase.
Figure 5.
AT ZERO CROSSING
DETERMINATED
TC7109A RUN/HOLD Operation
DETECTION
Table 1. TC7109A Direct Mode Timing Requirements
data accessing techniques may be used, as shown in the
"Interfacing" section. (See Figure 6 and Table 1.)
conversion cycle by monitoring the STATUS output. This
prevents accessing data while it is being updated and
eliminates the acquisition of erroneous data.
Symbol
t
t
t
t
t
t
HIGH-BYTE
BEA
DAB
DHB
CEA
DAC
DHC
LOW-BYTE
AS INPUT
AS INPUT
AS INPUT
CE/LOAD
ANALOG-TO-DIGITAL CONVERTERS
The access of data should be synchronized with the
MAX 2041 COUNTS
MIN 1790 COUNTS
HBEN
DATA
DATA
LBEN
AUTO-ZERO
Figure 6.
PHASE I
Description
Byte Enable Width
Data Access Time
From Byte Enable
Data Hold Time
From Byte Enable
Chip Enable Width
Data Access Time
From Chip Enable
Data Hold Time
From Chip Enable
t DAB
*
TC7109A Direct Mode Output Timing
= HIGH IMPEDANCE
TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE
t BEA
VALID
DATA
STATIC IN
HOLD STATE
7 COUNTS
Min Typ
t DAB
200
300
PHASE II
t DAC
INT
500
150
150
500
200
200
t CEA
VALID
VALID
DATA
DATA
Max
300
300
400
400
Units
t DHC
nsec
nsec
nsec
nsec
nsec
nsec