TC7109 TelCom, TC7109 Datasheet - Page 13

• Manufacturer Part Number: TC7109
• Description: 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: TelCom

12-BIT P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
Oscillator
an RC or crystal oscillator. The OSCILLATOR SELECT
input optimizes the internal configuration of the oscillator for
RC or crystal operation. The OSCILLATOR SELECT input
is provided with a pull-up resistor. When the OSCILLATOR
SELECT input is HIGH or left open, the oscillator is config-
ured for RC operation. The internal clock will be the same
frequency and phase as the signal at the BUFFERED
OSCILLATOR OUTPUT. Connect the resistor and capaci-
tor as in Figure 10. The circuit will oscillate at a frequency
given by f = 0.45/RC. A 100 k resistor is recommended for
useful ranges of frequency. The capacitor value should be
chosen such that 2048 clock periods are close to an integral
multiple of the 60 Hz period for optimum 60 Hz line rejection.
capacitors and a feedback device are added to the oscillator.
In this configuration, the oscillator will operate with most
crystals in the 1 to 5 MHz range with no external components
(Figure 11). The OSCILLATOR SELECT input LOW inserts
The oscillator may be overdriven, or may be operated as
With OSCILLATOR SELECT input LOW, two on-chip
CE/LOAD AS OUTPUT
TELCOM SEMICONDUCTOR, INC.
INTERNAL CLOCK
INTERNAL LATCH
HIGH-BYTE DATA
STATUS OUTPUT
LOW-BYTE DATA
INTERNAL MODE
POSITIVE TRANSITION
CAUSES ENTRY INTO
MODE INPUT
SEND INPUT
UART MODE
HBEN
LBEN
UART
NORM
= DON'T CARE
Figure 9. TC7109A Handshake Triggered by MODE Input
SENSED
SEND
STATUS OUTPUT UNCHANGED
DATA VALID
= THREE-STATE
IN UART MODE
HIGH IMPEDANCE
SENSED
a fixed 58 divider circuit between the BUFFERED OSCIL-
LATOR OUTPUT and the internal clock. A 3.58 MHz TV
crystal gives a division ratio providing an integration time
given by:
33.33 ms, which will give better than 40 dB, 60 Hz rejection.
The converter will operate reliably at conversion rates up
to 30 per second, corresponding to a clock frequency of
245.8 kHz.
TOR OUTPUT should be left open, and the overdriving
signal should be applied at the OSCILLATOR INPUT. The
internal clock will be of the same duty cycle, frequency and
phase as the input signal. When the OSCILLATOR SELECT
is at GND, the clock will be 1/58 of the input frequency.
SEND
t = (2048 clock periods)
The error is less than 1% from two 60 Hz periods, or
When the oscillator is to be overdriven, the OSCILLA-
DE PHASE III
DATA VALID
ZERO CROSSING OCCURS
= THREE-STATE
WITH PULL-UP
SENSED
ZERO CROSSING DETECTED
LATCH PULSE INHIBITED
IN UART MODE
SEND
3.58 MHz
58
TERMINATES
UART MODE
= 33.18 ms
TC7109A
TC7109
3-103
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