LM1246AAA National Semiconductor, LM1246AAA Datasheet - Page 31

• Manufacturer Part Number: LM1246AAA
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM/ 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

ATT2C0n
ATT2C1n
ATT2C2n
ATT2C3n
ATT4C0n
ATT4C1n
ATT4C2n
ATT4C3n
ATT4C4n
ATT4C5n
ATT4C6n
ATT4C7n
LM1246 Address Map
When reading, it is OK to read only one, two, or all three bytes. When writing more than one 2-color attribute using the auto
increment feature, all four bytes must be written. When writing, bytes 0 through 2 must be written in order. Bytes 0 through 2 will
take effect after byte 2 is written. Since byte 3 contains all reserved bits, this byte may be written, but will have no effect. Any bits
marked as “X” are reserved and should be written to with zeros and should be ignored when the register is read.
FOUR-COLOR ATTRIBUTE RAM
This address range (0x8500–0x857F), contains the attribute lookup tables used for displaying four-color characters. There are 16
groups of 8 bytes each according to the format shown in Table 17. LM1246 Four-Color Attribute Registers. The attributes are
stored starting with Color 0 (background) and each color is stored red first, green second and then blue. They may be written or
read using the following address format:
When writing, bytes 0 through 2 must be written in order and bytes 4 through 6 must be written in order. Bytes 0 through 2 will
take effect after byte 2 is written. Bytes 4 through 6 will take effect after byte 6 is written. Since bytes 5 and 7 contain all reserved
bits, these bytes may be written, but no effect will result. When reading, it is OK to read only one, two, or all three bytes. If writing
more than one 4-color attributes using the auto increment feature, all eight bytes must be written. Any bits marked as “X” are
reserved and should be written to with zeros and should be ignored when the register is read.
Building Display Pages
THE OSD WINDOW
The Display Page RAM contains all of the 9-bit display
character codes and their associated 4-bit attribute codes,
and the special 13-bit page control codes — the End-Of-Line,
Skip-Line parameters and End-Of-Screen characters. The
LM1246 has a distinct advantage over many OSD Genera-
tors in that it allows variable size and format windows. The
window size is not dictated by a fixed geometric area of
RAM. Instead, 512 locations of 13-bit words are allocated in
RAM for the definition of the windows, with special control
codes to define the window size and shape.
Window width can be any length supported by the number of
pixels per line that is selected divided by the number of
pixels in a character line. It must be remembered that OSD
characters displayed during the monitor blanking time will
Register
Register
0x8440 + 4n
8500 + (n*8)
Address
Address
+1
+2
+3
+1
+2
+3
+4
+5
+6
+7
TABLE 17. LM1246 Four-Color Attribute Registers
TABLE 16. LM1246 Two-Color Attribute Registers
where: N = Attribute number (0x0 ≤ N ≤ 0xF)
where: N = Attribute number (0x0 ≤ N ≤ 0xF)
(Continued)
B = Attribute byte number (0x0 ≤ B ≤ 0x3)
B = Attribute byte number (0x0 ≤ B ≤ 0x7)
Address = 0x8440 + (N * 0x4) + B
Address = 0x8500 + (N * 0x8) + B
C1B[0]
C1B[0]
C3B[0]
D7
D7
X
X
X
X
X
X
C0B[1:0]
C0B[1:0]
C2B[1:0]
D6
D6
X
X
X
X
X
X
31
not be displayed on the screen, so the practical limit to the
number of horizontal characters on a line is reduced by the
number of characters within the horizontal blanking period.
The EOS code tells the OSD generator that the character
codes following belong to another displayed window at the
next window location. An EOS code may follow normal char-
acters or an SL code, but never an EOL control code,
because EOL is always followed by an AC plus an SL code.
WRITING TO THE PAGE RAM
The Display Page RAM can contain up to 512 of the above
listed characters and control codes. Each character, or con-
trol code will consume one of the possible 512 locations. For
convenience, a single write instruction to bit 3 of the Frame
Control Register (0x8400) can reset the page RAM value to
all zero. This should be done at power up to avoid unpre-
dictable behaviour.
Display Window 1 will also start at the first location (corre-
sponding to the I
C1G[2:0]
C1G[2:0]
C3G[2:0]
D5
D5
X
X
X
X
C0G[2:0]
C0G[2:0]
C2G[2:0]
D4
D4
X
X
X
X
EF[3:0]
EF[3:0]
2
C address 0x8000). This location must
D3
D3
X
X
X
X
C1R[2:0]
C1R[2:0]
C3R[2:0]
D2
D2
X
X
X
X
C0R[2:0]
C0R[2:0]
C2R[2:0]
D1
D1
X
X
X
C1B[2:1]
C1B[2:1]
C3B[2:1]
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C0B[2]
C0B[2]
C2B[2]
D0
D0
X
X
X