LM1246AAA National Semiconductor, LM1246AAA Datasheet - Page 33

• Manufacturer Part Number: LM1246AAA
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM/ 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

Building Display Pages
HALF RANDOM ADDRESS MODE
The Half Random Address mode allows different attribute and character codes to be sent within one transmission in the same
way as the Two Byte Communication mode. The entire 512-character Page ROM is fully accessible in this mode, without the need
to stop and restart transmission. The advantage of Half Random Addressing over the Two Byte mode is that the Page RAM
addresses do not have to be written to in a sequential order. However, the Page RAM addresses cannot be entirely random, as
they must be within one half of the Page RAM. A new transmission must be restarted to switch to another half of the Page RAM.
The Page RAM address is not automatically incremented in this mode. This mode is very useful for modifying character codes
and attributes in the first 256 locations of the Page RAM. The attribute byte is shown in Table 23. Half Random Address Mode,
and the sequence of transmitted bytes is shown in Table 24. Sequence of Transmitted Bytes. Either another LSB address &
attribute & character code or a STOP must follow after each character code.
FULL RANDOM ADDRESS MODE
The Full Random Address mode is very similar to the Half Random Address mode. However, the advantage is that the Page RAM
addresses can now be entirely random. There is no longer a restriction to only one half of the Page RAM. The Page RAM address
is not automatically incremented in this mode. This is very useful for modifying character codes and attributes anywhere in the
Page RAM without starting a new transmission sequence. The Full Random Address mode is the most flexible mode of
transmission. The attribute byte is shown in Table 25. Full Random Address Mode, and the sequence of transmitted bytes is
shown in Table 26. Sequence of Transmitted Bytes. Either another LSB address & MSB address & attribute & character code or
a STOP must follow after each character code.
Control Register Definitions
OSD INTERFACE REGISTERS
Frame Control Register 1:
HTD
X
X
X
autosize
ASZEN
TABLE 21. Two Byte Communication Mode
0
1
1
TABLE 22. Sequence of Transmitted Bytes
TABLE 24. Sequence of Transmitted Bytes
TABLE 26. Sequence of Transmitted Bytes
(Continued)
TABLE 23. Half Random Address Mode
TABLE 25. Full Random Address Mode
Fade
1
0
1
FEN
i/o
FRMCTRL1 (0x8400)
ATTRIBUTE Byte
ATTRIBUTE Byte
ATTRIBUTE Byte
CC[8]
CC[8]
CC[8]
trans
TD
33
CDPR
clear
win2
D2E
ATT[3:0]
ATT[3:0]
ATT[3:0]
win1
D1E
OSD
OsE
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