AD5251 Analog Devices, AD5251 Datasheet - Page 11

• Manufacturer Part Number: AD5251
• Description: (AD5251 / AD5252) Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers
• Manufacturer: Analog Devices

I
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/ W = 0, CMD/ REG = 0, EE/ RDAC = 0)
A4
0
0
0
0
0
:
0
RDAC/EEMEM WRITE
Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 7, and the
consecutive write operation is shown in Figure 8. In the
consecutive write operation, if the RDAC is selected and the
address starts at 00001, the first data byte goes to RDAC1 and
the second data byte goes to RDAC3. The RDAC address is
shown in Table 6.
While the RDAC wiper setting is controlled by a specific RDAC
register, each RDAC register corresponds to a specific EEMEM
location, which provides nonvolatile wiper storage functionality.
The addresses are shown in Table 7. The single and consecutive
write operations apply also to EEMEM write operations.
2
C INTERFACE DETAIL DESCRIPTION
A3
0
0
0
0
0
:
1
S
A2
0
0
0
0
1
:
1
0
RDAC SLAVE ADDRESS
1
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW
A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
S
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
0
0
1
1
SLAVE ADDRESS
A1
0
0
1
1
0
:
1
1
0
A
D
1
1
A
D
0
0 WRITE
1
0
A
D
1
A0
0
1
0
1
0
:
1
A
A
D
0
0 WRITE
0 REG
CMD/
REG
0
Figure 8. Consecutive Write Mode
A
Figure 7. Single Write Mode
RDAC INSTRUCTIONS
0
0 REG
CMD/
REG
RDAC
Reserved
RDAC1
Reserved
RDAC3
Reserved
Reserved
Rev. 0 | Page 11 of 28
AND ADDRESS
RDAC
EE/
0
INSTRUCTIONS
AND ADDRESS
A
4
RDAC
EE/
A
3
There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store a total of 12 bytes of information,
such as memory data for other components, look-up tables, or
system identification information.
In a write operation to the EEMEM registers, the device disables
the I
polling is required to determine the completion of the write
cycle. See EEMEM Write-Acknowledge Polling.
A
2
A
4
A
1
A
3
2
C interface during the internal write cycle. Acknowledge
A
0
A
2
A
A
1
Data Byte Description
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
A
0
RDAC1
DATA
A
ACKNOWLEDGE)
ACKNOWLEDGE)
(N BYTES +
(1 BYTE +
DATA
A
RDAC3
DATA
A/
A
P
A/
A
AD5251/AD5252
P