AD5251 Analog Devices, AD5251 Datasheet - Page 21

• Manufacturer Part Number: AD5251
• Description: (AD5251 / AD5252) Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers
• Manufacturer: Analog Devices

DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and WP are digital inputs for which pull-up
resistors are recommended to minimize the MOSFETs cross
conduction current when the driving signals are lower than
V
Figure 35 and Figure 36.
WP can be permanently tied to V
the write-protect feature is not used. If WP is left floating, an
internal current source pulls it low to enable write-protect. In
applications where the device is not being programmed on a
frequent basis, this allows the part to default to write-protect
after any one-time factory programming or field calibration
without the use of an on board pull-down resistor. Because
there are protection diodes on all these inputs, their signal levels
must not be greater than V
diodes.
MULTIPLE DEVICES ON ONE BUS
The AD5251/AD5252 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5251/AD5252s to be
operated on one I
AD1 and AD0 on each device must first be defined. An example
is shown in Table 12 and Figure 37. In I
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
DD
. SCL and WP have ESD protection diodes, as shown in
SCL
WP
Figure 36. Equivalent WP Digital Input
2
C bus. To achieve this result, the states of
INPUTS
Figure 35. SCL Digital Input
DD
GND
GND
to prevent forward biasing of the
DD
without a pull-up resistor if
V
V
2
C programming, each
DD
DD
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Table 12. Multiple Devices Addressing
AD1
0
0
1
1
TERMINAL VOLTAGE OPERATION RANGE
The AD5251/AD5252 are designed with internal ESD diodes
for protection; these diodes also set the boundary of the
terminal operating voltages. Positive signals present on
Terminal A, B, or W that exceed V
forward biased diode. Similarly, negative signals on Terminal A,
B, or W that are more negative than V
Figure 38). In practice, users should not operate V
V
V
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 38), it is important to
power-on V
B, and W. Otherwise, the diodes are forward-biased such that
V
the user’s circuit. Similarly, V
last. The ideal power-up sequence is in the following order:
GND, V
powering V
long as they are powered after V
WB
WA
DD
MASTER
/V
, and V
to be higher than the voltage across V
SS
Figure 38. Maximum Terminal Voltages Set by V
DD
are powered unintentionally and may affect the rest of
Figure 37. Multiple AD5251/AD5252s on a Single Bus
, V
WB
A
DD
SDA SCL
AD1
AD0
, V
SS
AD0
0
1
0
1
have no polarity constraint.
/V
, digital inputs, and V
R
B
U1
, V
P
SS
before applying any voltage to Terminals A,
W
V
, and the digital inputs is not important, as
DD
R
P
SDA SCL
AD1
AD0
Device Addressed
U1
U2
U3
U4
+5V
DD
U2
/V
DD
V
SS
/V
DD
DD
should be powered down
A
SS
are clamped by the
/V
SDA SCL
AD1
AD0
SS
.
AD5251/AD5252
B
are also clamped (see
/V
U3
DD
W
W
V
V
A
B
. The order of
DD
SS
to V
V
DD
DD
SDA
AD1
AD0
SS
and V
AB
, but V
, V
SCL
U4
SS
WA
, and
SDA
SCL
AB
,