EPM3064xxx Altera, EPM3064xxx Datasheet - Page 30
EPM3064xxx
Manufacturer Part Number
EPM3064xxx
Description
MAX 3000A Programmable Logic Device Family
Manufacturer
Altera
Datasheet
1.EPM3064XXX.pdf
(46 pages)
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MAX 3000A Programmable Logic Device Family Data Sheet
30
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Symbol
IN
IO
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
RD
COMB
IC
EN
GLOB
PRE
CLR
Table 19. EPM3064A Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
Min
1.3
0.6
–4
Max
0.6
0.6
1.8
0.4
1.5
0.6
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.7
0.6
1.2
0.6
1.0
1.3
1.3
Note (1)
Speed Grade
Min
2.0
1.0
–7
Max
1.1
1.1
3.0
0.7
2.5
1.0
0.0
1.3
1.8
6.3
4.0
4.5
9.0
4.0
1.2
0.9
1.9
1.0
1.5
2.1
2.1
Min
2.9
1.3
Altera Corporation
–10
Max
10.0
1.4
1.4
3.9
0.9
3.2
1.2
0.0
1.8
2.3
6.8
5.0
5.5
5.0
1.6
1.3
2.5
1.2
2.2
2.9
2.9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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