SAA7201H Philips Semiconductors, SAA7201H Datasheet - Page 17

• Manufacturer Part Number: SAA7201H
• Description: Integrated MPEG2 AVG decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Basically there is no restriction on the number of different
regions but because regions may not vertically overlap the
practical limit will be the number of lines within a field.
However, one should realize that each region requires its
own 128-bit region descriptor.
The display list will be scanned twice per frame, once for
each display field. The region descriptors should be
ordered properly in the external SDRAM, starting from the
graphics anchor address. The last descriptor in the list
must have the end of display list indicator set.
Multiple pixel bit-maps, CLUTs and map tables may be
stored in the external memory but per region only two
bit-maps (one for each fields) and two tables
(CLUT + map table) may be used. Obviously bit-maps and
tables may be shared by multiple regions.
Pixel data bit-maps can be described in 2, 4 or 8 bit/pixel
in either a direct bit-map or coded in a one-dimensional (H)
variable and run length encoded format according the
pixel-data-sub-block syntax as specified in Chapter
“References” and illustrated in Chapter “Appendix”.
The actual coding format is specified in the region
descriptor for each region thus allowing different coding
schemes within a picture.
During display the 2, 4 and 8 bit/pixel bit-maps will be
transformed, eventually with run length decoding, via a
table look-up mechanism into a 4, 16 or 256 different YUV
colours with 8-bit resolution for each component plus a
factor T for mixing of graphics and MPEG video.
In order to obtain maximum flexibility two cascaded tables
are active in this bit-map to pixel conversion as indicated
in Fig.10.
1997 Jan 29
handbook, full pagewidth
Integrated MPEG2 AVG decoder
8
8 LSBs
4 LSBs
4 LSBs
2 LSBs
2 LSBs
Fig.10 Bit-map to pixel conversion.
TABLE 4 to 8
TABLE 2 to 8
MAP
MAP
8
8
17
The tables are retrieved from the external memory just
before the region is going to be displayed. One table per
region can be updated and for small tables this occurs
during the horizontal blanking interval. However, updating
a 256 entry CLUT may take about one line period which
means that a spatial separation of one line with the
previous region is mandatory in this case. If the required
tables for a certain region are already stored in the local
memory, the table down load action can be skipped.
Additionally some special bits can be set in the region
descriptor.
Regions can also be defined in the vertical blanking
interval. In combination with 8 bit/pixel coding, arbitrary
test signals on 13.5 MHz grid can be programmed.
Possible application areas are teletext, closed caption,
wide screen signalling bits, Video Programming Signals
(VPS) and Vertical Interval Test Signals (VITS).
As indicated above multiple regions can be specified in a
display list which will be scanned sequentially every frame.
In case of stationary graphics no updates of the display list
are required, but the external CPU can update it
dynamically to achieve scrolling and/or fading of one or
more graphical boxes. The display list mechanism also
allows for non real time transfer of large bit-maps by
keeping that region out of the display list during loading.
Transparency shift: this parameter overrules the pixel
based transparency in order to support fading of the
entire graphical region.
Zoom: this parameter initiates horizontal pixel repetition.
It should be noted that a copy of pixels in vertical
direction can be achieved by pointing to a single bit-map
for both fields.
8
CLUT
8
8
8
8
MGD330
Y
U
V
T
Objective specification
SAA7201