SAA7371GP Philips Semiconductors, SAA7371GP Datasheet - Page 10

• Manufacturer Part Number: SAA7371GP
• Description: Digital servo processor and Compact Disc decoder CD7
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.4
7.4.1
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found.
1998 Jul 06
A sync coincidence detected; sync pattern occurs
588 1 EFM clocks after the previous sync pattern
A new sync pattern is detected within 6 EFM clocks of
its expected position.
Digital servo processor and
Compact Disc decoder (CD7)
Demodulator
F
RAME SYNC PROTECTION
Fig.5 Data slicer showing typical application components (for n = 4).
inputs
HF
100 nF
22 k
1 nF
1 nF
V
SSA
22 pF
22 k
100
nF
V SSA
HFREF
ISLICE
HFIN
I ref
10
1/2V DD
The PLL lock signal can be accessed via the SDA or
STATUS pins selected by register 2 and 7.
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
100 A
100 A
EFM
D
crystal
clock
DEMODULATION
V SS
V DD
Q
MBG397
DPLL
Product specification
SAA7371