Z89303 Zilog., Z89303 Datasheet

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Z89303

Manufacturer Part Number
Z89303
Description
DIGITAL TELEVISION CONTROLLER
Manufacturer
Zilog.
Datasheet
DC-4222-03
GENERAL DESCRIPTION
The Z89303/05/07 Digital Television Controllers are
application-specific controllers designed to provide
complete audio and video control of television receivers,
video recorders, with advanced on-screen display facilities.
The Z89303/05/07 are 24K, 16K and 12K ROM versions in
52-pin SDIP packages. The powerful 12 MHz Z89C00
RISC processor core allows the user to control the on-
board peripheral functions and registers using the standard
processor instruction set.
The extensive character attributes can be controlled in two
modes: by the on-screen display controller character
control mode for maximum display control flexibility, and
closed caption mode for optimum display of closed caption
text.
Closed caption text can be decoded directly from the
composite video signal with the assistance of the
processor's digital signal processing capabilities and
displayed on the screen. The character representation in
this mode allows for a simple attribute control through the
insertion of control characters, and each word of RAM
specifies two displayed characters.
The character control mode provides access to the full set
of attribute controls. Each word of RAM specifies a single
displayed character and basic character attributes, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that incude underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency. The 16-bit
display character representation allows the modification of
some key attributes on a character-by-character basis. A
character's pixel array is stored as a 16- or 18-word
representation in Character Graphics ROM (CGROM).
The ROM contents are referenced by a 16-bit word stored
in video RAM (VRAM) defining the character type and its
key attributes.
(10-10-94)
P R E L I M I N A R Y
P
C
Z89303/05/07
DIGITAL TELEVISION CONTROLLER
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry standard I
Additional hardware provides the capability to display two
times normal size characters. The smoothing logic
contained in the on-screen display circuit improves the
appearance of larger fonts. Fringing circuitry can be
activated to improve the visibiity of text by surrounding the
character lines with a one-pixel border.
RGB outputs provide the direct video signals, and a
blanking output is provided to control the video multiplexor.
Dot clock and verticle line synchronization are normally
obtained from H_FLYBACK and V_FLYBACK, but can be
generated by the Z89303/05/047, and driven to the external
deflection unit through the bidirectional SYNC ports when
external video synchronization signals are not present.
User control can be monitored through the keypad scanning
port, or the 16-bit remote control capture register. Receiver
functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
All nine PWM ports are available in the 52-pin package.
The Z89303/05/07 has two internal 12 MHz VCOs that are
referenced to a 32 KHz internal oscillator to provide the
system clock. In Sleep mode, the controller uses the 32
KHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP mode when main power is not available for
minimal power consumption.
RELIMINARY
USTOMER
P
ROCUREMENT
S
PECIFICATION
2
C port.
CPS DC-4222-03
1

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Z89303 Summary of contents

Page 1

... All nine PWM ports are available in the 52-pin package. The Z89303/05/07 has two internal 12 MHz VCOs that are referenced KHz internal oscillator to provide the system clock. In Sleep mode, the controller uses the 32 KHz clock for the system clock to reduce power consumption ...

Page 2

... Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Note: Shaded pin functions not available on 40-pin device. OSD BLANK HALFBLNK Port0F ROM Note: Z89307 12K x 16 has 12K words of ROM. 16K x 16 Z89305 has 16K words. 24K x 16 Z89302/03 has 24K words. Z89303/05/07 ...

Page 3

... Port14/B<0> Port15/B<1> Port16/SCLK Port0A 25 Port0B 26 27 52-Pin Shrink DIP Configuration CPS DC-4222-03 PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 ADC5 CVI/ADC0 LPF XTAL2 AN GND XTAL1 AN VCC /Reset Port0F/HalfBlnk Port17/ADC1 Blank VSync HSync Port0D Port0C Z89303/05/07 3 ...

Page 4

... Z89303/05/07 52-Pin 17,38 10,40 2 44,11,12,6,35,43 –,1 52,51,50,49, 48,47,46,45 36,5,28,27,26,25, 16,15,14,13,12, 11,9,8,7,6 4,3,35,24,23,22, 21,20,19, 31,32, 23,22,21, 18,15 Z89303/05/07 CPS DC-4222-03 Configuration Direction Reset PWR PWR I I nAI BOD BOD ...

Page 5

... Bit = 10 Bit = 01 Bit = 00 70 Level, 10pf Load Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 70 Level, 10pf Load 32K Oscillator Recommended Circuit Z89303/05/07 CPS DC-4222-03 Limit 4.55 V +/– 0.25 V 3.205V +/– 0.2 V 1.95 V +/– 0.15 V 0.65 V +/– 0.1 V < 50 nsec Limit 3.90 V +/– 0.25 V 2.90 V +/– 0.2 V 1.90 V +/– 0.15 V 0.1 V +/– ...

Page 6

... V 1 –2.0 3.5 CC 3.0 0.75 0.5 150 90 –3.0 3.0 0.01 100 6 0 700 300 300 100 Z89303/05/07 CPS DC-4222-03 Conditions V V Digital Inputs V Analog Inputs (A/D0...A/D4) V All Push-Pull Digital Output V Open-Drain PWM Outputs (PWM1...PWM8) One Pin All Pins One Pin All Pins C C Units Conditions PWM0 ...

Page 7

... C bus interface are defined by related specifications of the bus interface 32.768 KHz OSC Min Max Typical 16 100 32 12 0.8 1.2 = 32.768 KHz OSC Min Max 5TPC 5.5 12.5 0.15 1.5 – 2.0 Z89303/05/07 CPS DC-4222-03 Units Typical Units 1 0 ...

Page 8

... Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Z89303/05/07 CPS DC-4222-03 ...

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