Z89323 Zilog., Z89323 Datasheet
Z89323
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Z89323 Summary of contents
Page 1
... To support a wide variety of development needs, the Z893X3 DSP product family features the cost-effective Z89323 with 8 Kwords of on-chip ROM, and the Z89373, a 16-MIPS OTP version of the Z89323, ideal for prototypes and early production builds. For systems requiring more than 8 Kwords of program memory, the Z89393 device can address Kwords of external program memory ...
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... Z89321/371/391 devices, providing users, who can benefit from increased integration and reduced system cost, an easy migration path from one DSP product to the next. Throughout this specification, references to the Z89323 device applies equally to the Z89373 and Z89393, unless otherwise specified. PD0-15 ...
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... PIN DESCRIPTION EXT3/P03 EXT4/P04 VSS EXT5/P05 EXT6/P06 EXT7/P07 INT1/P21 EXT8/P08 EXT9/P09 VSS EXT10/P010 Figure 2. 44-Pin PLCC Z89323/373 Pin Configuration Table 1. 44-Pin PLCC Z89323/373 Pin Description No. Symbol Function 1 P20/INT0 Port 2 0/Interrupt 0 2 EXT12/P012 Ext Data 12/Port EXT13/P013 Ext Data 13/Port 0 13 ...
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... SK/P15 20 P27 21 EXT8/P08 22 EXT9/P09 23 24 VSS 25 EXT10/P010 VSS Figure 3. 68-Pin PLCC Z89323/373 Pin Configuration Z89323/373 68-Pin PLCC Z89323/373/393 ...
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... Table 2. 68-Pin PLCC Z89323/373 Pin Description No. Symbol Function 1 P12/SIN Port 1 2/Serial Input 2 P20/INT0 Port 2 0/Interrupt 0 3 EXT12/P012 Ext Data 12/Port EXT13/P013 Ext Data 13/Port Power 6 EXT14/P014 Ext Data 14/Port Ground EXT15/P015 Ext Data 15/Port 0 15 ...
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... PIN DESCRIPTION (Continued) EXT3/P03 EXT4/P04 VSS EXT5/P05 EXT6/P06 EXT7/P07 INT1/P21 EXT8/P08 EXT9/P09 VSS EXT10/P010 Figure 4. 44-Pin QFP Z89323/373 Pin Configuration Table 3. 44-Pin QFP Z89323/373 Pin Description No. Symbol Function 1 EXT3/P03 Ext Data 3/Port EXT4/P04 Ext Data 4/Port Ground ...
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... VSS 9 VCC 10 EXT5/P05 11 P13/SOUT 12 EXT6/P06 13 P14/SS 14 EXT7/P07 15 P15/SK 16 P27 17 EXT8/P08 18 EXT9/P09 19 VSS 20 P33 Figure 4a. 80-Pin QFP Z89323/373 Pin Configuration DS95DSP0101 Q4/ Z89323 80-Pin QFP Z89323/373/393 16 IGITAL IGNAL ROCESSORS 60 P37 59 WAIT 58 P25/UI2 57 P22/UO0 56 P26 55 CLKO 54 ...
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... PIN DESCRIPTION (Continued) Table 4a. 80-Pin QFP Z89323/373 Pin Description No. Symbol Function Connection 2 EXT15/P015 Ext Data 15/Port XTEN Ext Enable Connection 5 EXT3/P03 Ext Data 3/Port P32 Port3 2 7 EXT4/P04 Ext Data 4/Port Ground ...
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... SK/P15 16 P27 17 PA12 18 EXT8/P08 19 PA13 20 EXT9/P09 21 PA14 22 VSS 23 PA15 24 EXT10/P010 25 VSS Figure 5. 100-Pin QFP Z89393 Pin Configuration DS95DSP0101 Q4/ Z89393 100-Pin QFP Z89323/373/393 16 IGITAL IGNAL ROCESSORS 75 VSS 74 /RES 73 PD15 72 WAIT 71 PD14 70 P25/UI2 69 PD13 68 P22/UO0 67 PD12 ...
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... EXT14/P014 Input Input Output Input 9 9 EXT15/P015 Input 100 /PAZ Z89323/373/393 16 IGITAL IGNAL ROCESSORS Function Direction Halt Execution Input Ext Address 0 Output Program Data 8 Input Ext Address 1 Output Program Data 9 Input ...
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... SIN/SOUT. When enabled, these pins control SPI input and output. AN0-AN3. These pins are used for Analog-to-Digital converter input. /INT2 ANGND and ANVCC. Analog to Digital ground and power 1FFDH supply. FFFDH Z89323/373/393 16 IGITAL IGNAL ROCESSORS The user output value is the ...
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... Internal ROM is mapped from 0000H to IFFFH, and the highest location for program is IFFBH. Internal Data RAM. The Z89323 has an internal 512 x 16- bit word data RAM organized as two banks of 256 x 16-bit words each: RAM0 and RAM1. Each data RAM bank is addressed by three pointers: Pn 0-2) for RAM0 and Pn 0-2) for RAM1 ...
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... REGISTERS The internal registers of the Z89323/373/393 are defined below: Register Register Definition P Output of Multiplier, 24-bit X X Multiplier Input, 16-bit Y Y Multiplier Input, 16-bit A Accumulator, 24-bit SR Status Register, 16-bit Pn:b Six Ram Address Pointers, 8-bit each P C Program Counter, 16-bit EXT 0 EXT 1 EXT 2 ...
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... C UI1 UI0 SH3 OP IE UO1 UO0 S12 S11 S10 Figure 7. Status Register Z89323/373/393 16 IGITAL IGNAL ROCESSORS RPL Ram Loop Pointer Size 256 ...
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... Ext3-user Port0 Ext4-user Port1/Port2 Port3 A/D_ch1 A/D_ch2 Bank/Int_status Bank/Int_status 6-12 13 A/D control Timer0 control Timer0 load Timer0 Timer0 pr. load Timer0 prescaler A/D_ch0 A/D_ch0 Bank/Int_status Bank/Int_status Z89323/373/393 16 IGITAL IGNAL ROCESSORS 3 4 Ext0-user Ext0-user Ext1-user Ext1-user Ext2-user Ext2-user SPI data Ext3-user Ext4-user Ext4-user ...
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... Wait State. EXT7 is always internal register, therefore no Wait State is needed for EXT7. Note: When the programmer switches banks it is important to change the Wait State mapping of the EXT registers to match the desired Wait State mapping of the new bank. Z89323/373/393 16 IGITAL ...
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... D15 D14 D13 D12 D11 D10 DS95DSP0101 Q4/ Figure 8a. Bank 15/EXT3 Register Z89323/373/393 16 IGITAL IGNAL ROCESSORS D1 D0 Bits Wait-State EXT0 Bits Wait-State EXT1 Bits Wait-State EXT2 Bits Wait-State EXT3 ...
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... Though the ADC will function for a smaller input voltage and voltage reference, the noise and offsets remain constant during the specified electrical range. The errors of the converter will increase and the conversion time may also take slightly longer due to smaller input signals. Z89323/373/393 16 ...
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... Multiplexer DS95DSP0101 Q4/ INT0 Timer Start Converter A/D Prescaler VREF Flash Sample A/D and Converter Hold AGND Channel Select Figure 9. ADC Architecture Z89323/373/393 16 IGITAL IGNAL A/D Controller Register Internal 4x8 Bus Result Register Dual A/D Channel Register Scan ...
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... ADIE=1. A value of 0 sets the Interrupt after the first A/D conversion is complete. A value of 1 sets the Interrupt after the fourth A/D conversion is complete. ADIE (bit 10). This is the ADC Interrupt Enable. A value of 0 disables setting the ADC Interrupt. A value of 1 enables setting the ADC Interrupt. Z89323/373/393 16 ...
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... CMOS Switch on Resistance Ref Ref Ref Figure 12. Input Impedance of ADC Z89323/373/393 16 IGITAL IGNAL ROCESSORS 31 CMOS Digital Comparators 21 ...
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... FUNCTIONAL DESCRIPTION (Continued Z89323/373/393 16 IGITAL IGNAL ROCESSORS DS95DSP0101 Q4/95 ...
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... TIMER/COUNTERS The Z89323/373/393 has two 16-bit Timer/Counters that can be independently configured to operate in various modes. Each is implemented as a 16-bit Load Register (TMLR) and a 16-bit down counter (TMR). Timer/Counter inputs can be selected from among UI0 or UI1 pins and outputs from among UO0 or UO1 pins. The Timer/Counter clock is a scaled version of system clock ...
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... MODE 11. The Timer/Counter is configured to count the number of input edges (up to 65,535 time window set by the second timer. Edges are counted until the second timer under flows. Input edges may be selected as rising or falling or both. Z89323/373/393 16 ...
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... Timer Control Register (TCTL DS95DSP0101 Q4/ Figure 15. Register Bit Fields Z89323/373/393 16 IGITAL IGNAL Timer/Counter 0 Timer/Counter disabled (default) 1 Timer/Counter enabled Input Select 00 Inputs have no effect 01 Reserved 10 UI0 Pin 11 UI1 Pin ...
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... However, writing to TPR is different than writing to an ordinary register. A write to TPR Register causes the lower 8-bit contents of TPLR Register to be written into it, causing 0 the Prescaler to be retriggered. Any data on DSP’s Memory Data (MD) Bus is ignored during a write to TPR. 7 Z89323/373/393 16 IGITAL ...
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... TMLR Register, or retriggered by writing directly to TMR Register Prescaler Zeros Reload Value Clock TPR 8-Bit Counter Figure 16. Prescaler Block Diagram 15 TMLR Register 15 TMR Register 16-Bit Counter Figure 17. Counter/Timer Block Diagram Z89323/373/393 16 IGITAL IGNAL 0 TPLR Register DIV TMCLK U00 ...
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... EXT bus, these I/O pins can be allocated to 16-bit general-purpose I/O port (P0), the special signals port (P1) or additional port (P3). The 80-pin PQFP package supports I/O pins. Table 9. Various Package I/O Port Allocation 68-Pin PLCC EXT,P0 EXT,P0 P1* P2* Z89323/373/393 16 IGITAL IGNAL Count Value (Down-Counter) ...
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... Bank 15/Ext 1, has specified bits to enable Port 0 and determine whether Port 0 is globally configured as open-drain outputs Figure 19. Port 0 Control Register R 500 kOhms Figure 20. Port 0, 1 and 2 Configuration Z89323/373/393 16 IGITAL IGNAL ROCESSORS Port I/O Direction 0 = Output ...
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... Bank0/EXT5 (Least Significant Bit) acts as the data I/O register. Bank15/EXT1 serves as the Port1 direction control register. Port 1 can also be programmed to provide special I/O functions. Table 10. Port 1 Bit Function Selection Figure 21. Bank15/EXT1 Register Z89323/373/393 16 IGITAL IGNAL Then Else INT2 P10 CLKOUT P11 ...
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... Figure 22. Bank15/EXT2 Register supported in the 100-pin ICE chip PQFP package, therefore this port is not supported in the Z893x3 emulator, recommended in cases when the other I/O ports can support the I/O requirements. Z89323/373/393 16 IGITAL IGNAL Then Else INT0 P20 INT1 P21 ...
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... Overrun (RxCharOverrun) flag is set in the SCON Register and the data in the RxBUF Register is overwritten. Bank15/Ext4 (LSB) Reg Figure 23. SPI Control Register (SCON) Bank 0/Ext 3 (LSB) Reg Figure 24. SPI TXRXDATA Register Z89323/373/393 16 IGITAL IGNAL ...
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... RxBUF Register, Receive Character Overrun (RxCharOverrun) occurs. Since there is no need for clock control in slave mode, bit D1 in the SPI Control Register is used to log any RxCharOverrun Figure 25. SPI Timing Z89323/373/393 16 IGITAL IGNAL ROCESSORS ...
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... STOP CLOCK - Oscillator running Khz 0 4) STOP CLOCK 1 5) EXTERNAL CLOCK source * VCO :2 STOP_VCO 8-Bit :2 Divider PLL Divider Clock Source Bank4 / Ext5 Figure 26. PLL Functional Block Diagram Z89323/373/393 16 IGITAL IGNAL ROCESSORS 00 01 MUX System MUX Clock ...
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... Programmable PLL Divider Register VCO Frequency = Bits 15 Crystal Frequency (32 kHz) 39 (9.984 MHz) < Bits 15-8 < 158 (40.448 MHz) Figure 27. PLL Register Z89323/373/393 16 IGITAL IGNAL In this mode of operation the on chip from the reset vector address after D1 D0 STOP_OSC 0 : Oscillator Running ...
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... Banks) to determine which interrupt occurred and decides on the relative priority. The Interrupt Status Register can be used for polling interrupts mode Figure 28. Interrupt Allocation Register Z89323/373/393 16 IGITAL IGNAL D1 D0 IINT0 Source 0000 : A/D Finish 0001 : SPI ...
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... XDATA 16 IGITAL IGNAL DDATA Mult. (24) Shift Unit * * Options Bit Right 3 Bits Right No Shift MUX 1 Bit Left Arithmetic Logic Unit (ALU) 24 Accumulator (24) Figure 30. ALU Block Diagram Z89323/373/393 P ROCESSORS 37 ...
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... The Call instruction pushes PC+2 onto the stack, and the RET instruction pops the contents of the stack to the PC. User Inputs. The Z89323 has two inputs, UI0 and UI1, which may be used by Jump and Call instructions. The Jump or Call tests one of these pins and if appropriate, jumps to a new location ...
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... D8 16 IGITAL IGNAL %FF RAM Pointers P0:1 P1:1 P2:1 % %00 Data Pointers D0:0 %0321 D0:1 D1:0 D1:1 D2:0 D2:1 D3:0 D3:1 Each of the following instructions load %1234 into the Accumulator: LD A,@@P1:0 LD A,@D0 RAM Pointer Register Operation RAM Bank Figure 32. Indirect Register Z89323/373/393 P ROCESSORS 39 ...
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... located in the RAM bank, which can then be used to point to a program memory location. This facilitates downloading lookup tables and other instructions from program memory to RAM Figure 34. Short Form Direct Address Z89323/373/393 16 IGITAL IGNAL ROCESSORS D1 D0 RAM Address ...
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... When the short form direct mode is selected, EXT3 00000-01111 or 10000-11111 are used as RAM addresses. EXT4 EXT5 EXT6 EXT7 Figure 35. General Instruction Format Z89323/373/393 16 IGITAL IGNAL ROCESSORS Meaning NOP + 1 –1/LOOP +1/LOOP P0:0 or P0:1 [2] P1:0 or P1:1 [2] P2:0 or P2:1 [2] Short Form Direct Mode D1 ...
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... TRUE UO0 UO1 Negative Condition 1 = Positive Condition Opcode DS95DSP0101 Q4/95 Z89323/373/393 P ROCESSORS ...
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... Figure 39. Branching Format Figure 40. Flag Modification Format Z89323/373/393 16 IGITAL IGNAL ROCESSORS 1st Word Condition Codes TRUE ---- UO0 UO1 C Z=0 ...
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... Pointer register Indirect with Loop Increment @@Pn:b Pointer Register Memory Indirect @Dn:b Data Register Memory Indirect @@Pn:b–LOOP Pointer Register Memory Indirect with Loop Decrement @@Pn:b+LOOP Pointer Register Memory Indirect with Loop Increment @@Pn:b+ Pointer Register Memory Indirect with Increment Z89323/373/393 16 IGITAL IGNAL ROCESSORS DS95DSP0101 Q4/95 ...
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... RAM pointer. one of its addressing modes, the instruction will only execute if the condition is true. Code NU1 UGE ULT Z Z89323/373/393 16 IGITAL IGNAL ROCESSORS Description Not User One Not zero Overflow Plus (Positive) ...
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... A,<limm> A,<memi n d> A,<direct> A,<regind> A,<hwregs> A, <simm> <cc>,<direct> <direct> None None None A,<pregs> A,<dregs> A,<memi n d> A,<direct> A,<regind> A,<hwregs> A< m> A, <simm> <cc>A, A <cc>,A A <cc>,<direct> <direct> Z89323/373/393 16 IGITAL IGNAL ROCESSORS Cycles Examples 1 1 ABS NC ABS ADD A,P0 ADD A,D0 ADD A,#%1234 ...
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... Note: If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register. Note: <hwregs> for src1 cannot be X. Note: For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank switch> defaults to ON. Z89323/373/393 16 ...
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... None A, <pregs> A, <dregs> A, <limm> A, <memind> A, <direct> A, <regind> A, <hwregs> A, <simm> <pregs> <dregs> <regind> <hwregs> <pregs> <dregs> <regind> <hwregs> < m> <acci n d> <memi n d> None <cc>,A A <cc>,A A Z89323/373/393 16 IGITAL IGNAL ROCESSORS Cycles Examples 1 1 MPYS A,@P0:0 1 MPYS A,@P1:0,OFF 1 1 MPYS @P1:1,@P2:0 1 MPYS @P0:1,@P1:0, NEG MI,A 1 ...
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... A, <memind> A, <direct> A, <regind> A, <hwregs> A, <simm> the direction of the switch. These keywords are referenced in the instruction descriptions through the <bank switch> symbol. The most notable capability this provides is that a source operand can be multiplied by itself (squared). Z89323/373/393 16 IGITAL IGNAL ROCESSORS Cycles ...
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... From Output Under T est Standard Temp + Condition Min 5. –100 Z89323/373/393 16 IGITAL IGNAL + 9.1 kOhm Figure 41. Test Load Diagram Extended Temp T = – Max. Min. Max 2.7 ...
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... Min. Max TCY 1000 TCY Z89323/373/393 16 IGITAL IGNAL ROCESSORS Units ...
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... VALO +2.5 ANGND 2.5 Standard Temp + Condition Min. Max 5. 2 –100 Z89323/373/393 16 IGITAL IGNAL ROCESSORS Max Units Bits 1 LSB 1 LSB 5.5 Volts MHz VAHI Volts ...
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... TCY 1500 TCY Min. Typical 8 0.5 0.5 4.5 5 VALO 2 5 VALO +2.5 ANGND ANVCC –2.5 2.5 Z89323/373/393 16 IGITAL IGNAL ROCESSORS Units ...
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... EXT(15:0) CLOCK WSET WAIT /DS EA(2:0) RD//WR EXT(15: TCY DSHOLD EAHOLD RDHOLD RDSET Data In Figure 42. Read Timing TCY WHOLD Valid Address Out Data In Figure 43. Read Timing Using WAIT Pin Z89323/373/393 16 IGITAL IGNAL ROCESSORS Tr Tf CPW DS95DSP0101 Q4/95 ...
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... CLOCK WAIT /DS EA(2:0) RD//WR EXT(15:0) DS95DSP0101 Q4/ TCY DSHOLD EAHOLD Valid Address Out EAHOLD WRHOLD WRVALID Data In Figure 44. Write Timing TCY WHOLD WSET Valid Address Out Data In Figure 45. Write Timing Using WAIT Pin Z89323/373/393 16 IGITAL IGNAL ROCESSORS 55 ...
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... HALT TCY INTSET INTWidth Fetch N Fetch N +1 Fetch Int_Addr Execute N –1 Execute N CALL Int Routine Figure 46. Interrupt Timing TCY Figure 47. HALT Timing Z89323/373/393 16 IGITAL IGNAL ROCESSORS Fetch I Fetch I +1 Execute Int Routine DS95DSP0101 Q4/95 ...
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... The RAM and hardware registers are left intact during a warm reset. A cold reset will produce random data in these locations. The status register is set to zeroes in both cases. Figure 48. RESET Timing TCY Valid Valid PDSET PDHOLD Valid 16 IGITAL IGNAL Cycle 5 Code Exec Valid Valid Valid Z89323/373/393 P ROCESSORS 57 ...
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... PACKAGE INFORMATION 44-Pin PLCC Package Diagram 68-Pin PLCC Package Diagram Z89323/373/393 16 IGITAL IGNAL ROCESSORS DS95DSP0101 Q4/95 ...
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... DS95DSP0101 Q4/ 44-Pin QFP Package Diagram 80-Pin QFP Package Diagram Z89323/373/393 16 IGITAL IGNAL ROCESSORS 59 ...
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... PACKAGE INFORMATION (Continued 100-Pin QFP Package Diagram Z89323/373/393 16 IGITAL IGNAL ROCESSORS DS95DSP0101 Q4/95 ...
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... E = – +85 C Speed MHz MHz Environmental C = Plastic Standard Example: Z 89323 Z89323, 20 MHz, PLCC +70 C, Plastic Standard Flow Environmental Flow T emperature Package Speed / Bond Out Option* Product Number Zilog Prefix * MHz, 68-pin PLCC style package ...