CY8C25122 Cypress Semiconductor, CY8C25122 Datasheet - Page 72

• Manufacturer Part Number: CY8C25122
• Description: 8-Bit Programmable System-on-Chip (PSoC) Microcontrollers
• Manufacturer: Cypress Semiconductor

10.2
Table 61:
10.3
72
ACLK0
ACLK1
Acolumn0
Acolumn1
Acolumn2
Acolumn3
Signal
Analog System Clocking Signals
Array of Analog PSoC Blocks
Analog System Clocking Signals
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK0[2:0] bits in the Analog Clock Select Register (CLK_CR1).
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK1[2:0] bits in the Analog Clock Select Register (CLK_CR1).
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 0. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn0[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 1. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4.The
Acolumn1[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 2. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn2[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 3. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn3[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
Column 0
Analog
ACA00
ASB20
ASA10
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Figure 16: Array of Analog PSoC Blocks
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Column 1
ASA21
Analog
ACA01
ASB11
Definition
Column 2
Analog
ACA02
ASB22
ASA12
Column 3
Analog
ACA03
ASB13
ASA23
September 5, 2002