CY8C25122 Cypress Semiconductor, CY8C25122 Datasheet - Page 93
CY8C25122
Manufacturer Part Number
CY8C25122
Description
8-Bit Programmable System-on-Chip (PSoC) Microcontrollers
Manufacturer
Cypress Semiconductor
Datasheet
1.CY8C25122.pdf
(148 pages)
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10.10.2
10.10.2.1
FCap controls the size of the switched feedback capaci-
tor in the integrator.
ClockPhase controls the internal clock phasing relative
to the input clock phasing. ClockPhase affects the output
of the analog column bus which is controlled by the
AnalogBus bit in Control 2 Register (ASB11CR2,
ASB13CR2, ASB20CR2, ASB22CR2).
Table 72:
September 5, 2002
BMuxSCB
Bit #
POR
Read/
Write
Bit Name
ARefMux
A Inputs
B Inputs
REFLO
A Mux
REFHI
AGND
ASign
Registers
Analog Switch Cap Type B Block xx Control 0 Register
Analog Switch Cap Type B Block xx Control 0 Register
FCap
RW
7
0
φ
ClockPhase
2
+!BSW
φ
φ
1
2
Figure 25: Analog Switch Cap Type B PSoC Blocks
RW
6
0
0..31 C
0..31 C
ACap
BCap
φ
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
1
*BSW
ASign
RW
5
0
φ
2
+AutoZero
φ
!AutoZero
φ
1
2
+!BSW
*
φ
ACap[4]
1
*BSW
RW
4
0
ASign controls the switch phasing of the switches on the
bottom plate of the A capacitor. The bottom plate sam-
ples the input or the reference.
The ACap bits set the value of the capacitor in the A
path.
16,32 C
FCap
Power
ACap[3]
RW
3
0
φ
1
*AutoZero
φ
1
(φ
* FSW0
2
ACap[2]
+!AutoZero)
RW
2
0
* FSW1
ACap[1]
RW
1
0
AnalogBus*φ
0..31 C
Analog PSoC Blocks
CCap
CompBus
ACap[0]
RW
2
0
0
B
BQTAP
OUT
ABUS
CBUS
93
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