MC68020 Motorola, MC68020 Datasheet - Page 233
MC68020
Manufacturer Part Number
MC68020
Description
(MC68020 / MC68EC020) MICROPROCESSORS USERS MANUAL
Manufacturer
Motorola
Datasheet
1.MC68020.pdf
(306 pages)
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8.2.5 Jump Effective Address
The jump effective address table indicates the number of clock periods needed for the
processor to calculate the specified effective address. Fetch time is only included for the
first level of indirection on memory indirect addressing modes. The total number of clock
cycles is outside the parentheses; the number or read, prefetch, and write cycles is given
inside the parentheses as (r/p/w). These cycles are included in the total clock cycle
number.
B = Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing.
I
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
MOTOROLA
(An)
(d
(xxx).W
(xxx).L
(d
(d
(B)
(B,d
(B,d
([B],I)
([B],I,d
([B],I,d
([d
([d
([d
([d
([d
([d
16
8
16
16
16
16
32
32
32
= Index; 0, Xn
,An,Xn) or (d
,An)
,An,Xn) or (d
16
32
,B],I)
,B],I,d
,B],I,d
,B],I)
,B],I,d
,B],I,d
)
)
16
32
)
)
16
32
16
32
)
)
)
)
8
,PC,Xn)
16
,PC,Xn)
Address Mode
M68020 USER’S MANUAL
Best Case
10(1/0/0)
10(1/0/0)
10(1/0/0)
12(1/0/0)
12(1/0/0)
14(1/0/0)
16(1/0/0)
16(1/0/0)
0(0/0/0)
1(0/0/0)
0(0/0/0)
0(0/0/0)
3(0/0/0)
3(0/0/0)
3(0/0/0)
5(0/0/0)
9(0/0/0)
8(1/0/0)
Cache Case
12(0/0/0)
11(1/0/0)
13(1/0/0)
13(1/0/0)
13(1/0/0)
15(1/0/0)
15(1/0/0)
17(1/0/0)
19(1/0/0)
19(1/0/0)
2(0/0/0)
4(0/0/0)
2(0/0/0)
2(0/0/0)
6(0/0/0)
6(0/0/0)
6(0/0/0)
8(0/0/0)
Worst Case
12(0/1/0)
11(1/1/0)
14(1/1/0)
14(1/1/0)
14(1/1/0)
17(1/1/0)
17(1/1/0)
19(1/2/0)
21(1/2/0)
23(1/2/0)
2(0/0/0)
4(0/0/0)
2(0/0/0)
2(0/0/0)
6(0/0/0)
6(0/0/0)
6(0/0/0)
8(0/1/0)
8- 19
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