MC68HC705C Motorola, MC68HC705C Datasheet - Page 115

• Manufacturer Part Number: MC68HC705C
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

9.5.2 Mask Option Register 1
MC68HC705C8A — Rev. 2.0
MOTOROLA
Address:
SEC — Security Bit
IRQ — Interrupt Request Pin Sensitivity Bit
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
Mask option register 1 (MOR1) shown in
register that enables the port B pullup devices. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin.
See
PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0
Erased:
Reset:
Read:
Write:
This bit is implemented as an EPROM cell and is not affected by
reset.
IRQ is set only by reset, but can be cleared by software. This bit can
only be written once.
These EPROM bits enable the port B pullup devices.
4.3.3 Port B
1 = Security enabled
0 = Security off; bootloader able to be enabled
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
1 = Port B pullups enabled
0 = Port B pullups disabled
PBPU7
$1FF0
Bit 7
0
Figure 9-5. Mask Option Register 1 (MOR1)
EPROM/OTPROM (PROM)
PBPU6
Interrupts.
6
0
PBPU5
5
0
Unaffected by reset
PBPU4
4
0
PBPU3
Figure 9-5
3
0
EPROM/OTPROM (PROM)
PBPU2
2
0
is an EPROM
PBPU1
Control Registers
1
0
Technical Data
PBPU0/
COPC
Bit 0
0
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