MC68HC705C Motorola, MC68HC705C Datasheet - Page 99

• Manufacturer Part Number: MC68HC705C
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

8.4.6 Output Compare Registers
MC68HC705C8A — Rev. 2.0
MOTOROLA
Register Name and Address: Output Compare Register High — $0016
Register Name and Address: Output Compare Register Low — $0017
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL) shown in
planned TCMP pin action takes place. Writing to OCRH before writing to
OCRL inhibits timer compares until OCRL is written. Reading or writing
to OCRL after reading the timer status register clears the output
compare flag (OCF).
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
Reset:
Reset:
Read:
Read:
Write:
Write:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code
Figure 8-12. Output Compare Registers (OCRH and OCRL)
register.
Bit 15
Bit 7
Bit 7
Capture/Compare Timer
Bit 14
Bit 6
6
Bit 13
Bit 5
5
Unaffected by reset
Unaffected by reset
Bit 12
Bit 4
4
Bit 11
Bit 3
3
Bit 10
Bit 2
2
Capture/Compare Timer
Figure
Timer I/O Registers
Bit 9
Bit 1
1
Technical Data
8-12, the
Bit 0
Bit 8
Bit 0
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