LTC4088 LINER [Linear Technology], LTC4088 Datasheet - Page 20

• Manufacturer Part Number: LTC4088
• Description: High Effi ciency Battery Charger/USB Power Manager
• Manufacturer: LINER [Linear Technology]

LTC4088
APPLICATIO S I FOR ATIO
The long time constant of R1 and C1 prevent the current
from building up in the cable too fast, thus dampening
out any resonant overshoot.
Voltage overshoot on V
when connecting the LTC4088 to a lab power supply. This
overshoot is caused by long leads from the power supply
to V
V
long leads, and keep the voltage at V
cables are generally manufactured with the power leads in
close proximity, and thus fairly low parasitic inductance.
Board Layout Considerations
The Exposed Pad on the backside of the LTC4088 pack-
age must be securely soldered to the PC board ground.
This is the only ground pin in the package, and it serves
as the return path for both the control circuitry and the
synchronous rectifi er.
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitor, inductor, and output
capacitor be as close to the LTC4088 as possible and that
there be an unbroken ground plane under the LTC4088
20
BUS
BUS
can greatly reduce the parasitic inductance of these
. Twisting the wires together from the supply to
U
BUS
U
may sometimes be observed
Figure 6. Ground Currents Follow Their Incident Path
at High Speed. Slices in the Ground Plane Cause High
Voltage and Increased Emissions
BUS
W
to safe levels. USB
U
and all of its external high frequency components. High
frequency currents, such as the input current on the
LTC4088, tend to fi nd their way on the ground plane along
a mirror path directly beneath the incident path on the top
of the board. If there are slits or cuts in the ground plane
due to other traces on that layer, the current will be forced
to go around the slits. If high frequency currents are not
allowed to fl ow back through their natural least-area path,
excessive voltage will build up and radiated emissions will
occur (see Figure 6). There should be a group of vias directly
under the grounded backside leading directly down to an
internal ground plane. To minimize parasitic inductance,
the ground plane should be as close as possible to the
top plane of the PC board (layer 2).
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an additional offset
to the ideal diode of approximately 10mV. To minimize
leakage, the trace can be guarded on the PC board by
surrounding it with V
generally be less than one volt higher than GATE.
4088 F06
OUT
connected metal, which should
4088f